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ADMtek ADM5120 Datasheet

Home gateway controller
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ADM5120
HOME GATEWAY CONTROLLER
Datasheet
Version 1.13
ADMtek
com.tw
.
Information in this document is provided in connection with ADMtek products. ADMtek may make
changes to specifications and product descriptions at any time, without notice. Designers must not rely on
the absence or characteristics of any features or instructions marked "reserved" or "undefined". ADMtek
reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them
The products may contain design defects or errors known as errata, which may cause the product to deviate
from published specifications. Current characterized errata are available on request. To obtain the latest
documentation please contact you local ADMtek sales office or visit ADMtek's website at
http://www.admtek.com.tw
*Third-party brands and names are the property of their respective owners.
Copyright 2003 by ADMtek Incorporated All Rights Reserved.

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  • Page 1 ADM5120 HOME GATEWAY CONTROLLER Datasheet Version 1.13 ADMtek com.tw Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. ADMtek...
  • Page 2 Chapter 3 Function Description Chapter 4. Register Description Chapter 5 Electrical Packaging Chapter 6. Packaging Customer Support ADMtek Incorporated, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Sales Information Tel + 886-3-5788879 Fax + 886-3-5788871 ADM5120 V1.13...

  • Page 3: Revision History

    05 June 2003 13 June 2003 08 October 2003 29 October ADM5120 Version Change First release of ADM5120 3.4, 4.5, 4.6, 4.7, 4.8 and 5.3 sections added. Updated pin numbers. 1.11 Updated Table for Clock Speeds 1.12 2.2.5 Memory Bus : A[2] 2.2.10 PCI added CLK I/P...

  • Page 4: Table Of Contents

    PHY... 3-2 3.2.1 PHY Overview... 3-2 3.2.2 Link Detect ... 3-2 3.2.3 Auto-Negotiation... 3-2 3.2.4 Digital Adaptive Equalizer ... 3-2 3.2.5 Clock Recovery ... 3-3 ADM5120 ... 1-1 ... 1-3 ... 1-3 ... 1-5 ... 2-1 ... 2-4 UNCTION V1.13...
  • Page 5 FIQ_status, offset: 0x18... 4-3 4.2.10 IRQ_test_source, offset: 0x1c ... 4-3 4.2.11 IRQ_source_sel, offset: 0x20 ... 4-3 4.2.12 INT_level, offset: 0x24 ... 4-3 WITCH ONTROL WITCH ONTROL ADM5120 ... 3-4 ... 3-10 ONTROLLER ... 3-11 ... 4-1 ... 4-1 NTERRUPT EGISTERS ... 4-4 EGISTER ...
  • Page 6 Custom_pri1, offset 0x98 ... 4-18 4.4.40 Custom_pri2, offset 0x9c ... 4-18 4.4.41 PHY_cntl4, offset 0xA0 ... 4-19 4.4.42 Empty_cnt, offset 0xA4... 4-19 4.4.43 Port_cnt_sel, offset 0xA8 ... 4-19 4.4.44 Port_cnt, offset 0xAc... 4-19 4.4.45 Int_st, offset 0xB0... 4-20 ADM5120 V1.13...
  • Page 7 MPMC Status register, offset 004h... 4-38 4.7.4 MPMC Config register, offset 008h... 4-39 4.7.5 MPMC Dynamic Control register, offset 020h... 4-39 4.7.6 MPMC Dynamic Refresh register, offset 024h ... 4-40 ADM5120 ... 4-26 TATUS EGISTER TATUS EGISTERS ESCRIPTION ... 4-36 ...
  • Page 8 UART line control register, low byte, offset 10h ... 4-54 4.8.7 UART control register (UARTCR), offset 14h ... 4-54 4.8.8 UART flag register (UARTFR), offset 18h... 4-55 4.8.9 UARTIIR/UARTICR, offset 1ch ... 4-57 CHAPTER 5 ELECTRICAL SPECIFICATION... 5-1 BSOLUTE ADM5120 ... 4-52 ... 5-1 AXIMUM ATINGS V1.13...
  • Page 9 ... 5-2 IMING 5.3.1 SDRAM interface ... 5-2 5.3.2 Memory Bus Read Timing... 5-5 5.3.3 Memory Bus Write Timing ... 5-6 CHAPTER 6 PACKAGING ... 6-1 LASTIC ADM5120 ... 5-1 (BGA) 324- ... 6-1 RRAY (PQFP) 208- ... 6-2 V1.13...
  • Page 10 Figure 5-2 Active Command ... 5-3 Figure 5-3 Write Command ... 5-4 Figure 5-4 Read Command... 5-4 Table 2-1 ADM5120 324 BGA Pin Assignment... 2-2 Table 2-2 ADM5120 208PQFP Pin Assignments ... 2-3 Table 2-3 LED Program Table ... 2-6 Table 4-1 MPMC Registers Summary...

  • Page 11: Chapter 1 Product Overview

    ADM5120 is a high performance, highly integrated, and highly flexible SOC (System- On-Chip) that facilitates the functionalities of SOHO/SME Gateway, NAT Router, Print Server, WLAN Access Point, and VPN Gateway. ADM5120 enables the sharing of IP- based broadband services throughout the home/office using wired/wireless computers, entertainment equipment, printers, and other intelligent devices.

  • Page 12: Features

    ADM5120 Features ASIC Features Processor MIPS 4Kc CPU • Embedded cache, 8K-byte I- • cache, 8K D-cache Embedded memory management • unit (MMU) – 32-entry TLB, organized as 16 entry pairs 175 MHz/227 MIPS • Network 6 ports • – IEEE 802.3 Fast Ethernet –...
  • Page 13 ADM5120 Software Features Linux/ECOS (Embedded • Configurable OS) Real-Time OS Linux-based and ECOS-based • turn key support Telnet • IEEE 802.3 Ethernet Driver • IEEE 802.11 WLAN Driver • RS232 Driver for Console User • Interface DHCP Server/Client • PPP over Ethernet (PPPoE) •...

  • Page 14: Block Diagram

    GMAC multi-port 10/100 10/100 memory controller auto auto MDIX MDIX Figure 1-1 ADM5120 Block Diagram Advance High performance Bus Address Latch Enable Auto-Negotiation Advanced Peripheral Bus Advanced System Bus Application Specific Integrated Circuit BroadCast Back Pressure Bridge Protocol Data Unit...
  • Page 15 ADM5120 FIFO GPIO GPIOL GPIOM GPSI INTC INTX JTAG MDIO MDIX MIPS NRZI PQFP RISC RXDV SYSC ADMtek Inc. Flow Control First-In-First-Out Ground General Purpose I/O GPIO of groupL GPIO of groupM General Purpose Serial Interface Head-on-Line Interrupt Control Registers...

  • Page 16: Conventions

    ADM5120 UART VLAN Conventions 1.5.1 Data Lengths qword dword word byte nibble 1.5.2 Register Descriptions Register Type 1.5.3 Pin Descriptions Pin Type ADMtek Inc. Universal Asynchronous Receiver Transmitter Virtual LAN Wide Area Networks 64-bits 32-bits 16-bits 8 bits 4 bits...

  • Page 17: Chapter 2 Interface Description

    ADM5120 Chapter 2 Interface Description Pin Assignment 2.1.1 324BGA Ball assignment Pin name Ball VCCRG VCCRG VCCBIAS VCCBIAS VREF CONTROL VCCPLL 10. XI 11. GCRS 12. GCOL 13. G_TXD[7] 14. G_TXD[6] 15. G_TXD[5] 16. G_TXD[4] 17. G_TXD[3] 18. G_TXD[2] 19. G_TXD[1] 20.

  • Page 18: Table 2-1 Adm5120 324 Bga Pin Assignment

    75. VSS 76. VSS 77. VSS 78. VSS 79. VSS 80. VSS 81. VSS 82. VSS 83. VSS 84. VSS Table 2-1 ADM5120 324 BGA Pin Assignment Interface Description Ball Pin name Ball GNDR/T GNDR/T GNDR/T GNDR/T DVDD DVDD DVDD...

  • Page 19: 208Pqfp Pin Assignment

    ADM5120 Interface Description 2.1.2 208PQFP pin assignment Table 2-2 ADM5120 208PQFP Pin Assignments ADMtek Inc.

  • Page 20: Pin Description By Function

    ADM5120 Pin Description by Function ADM5120 pins are categorized into one of the following groups: Section 2.2.1 Network Media Connection Section 2.2.2 Clock for Network Section 2.2.3 LED Section 2.2.4 GMII/MII Management Section 2.2.5 Memory Bus Section 2.2.6 SDRAM Control Signals Section 2.2.7 UART...

  • Page 21: Network Media Connection

    ADM5120 2.2.14 Power and Ground Section 2.2.15 Regulator Interface Section Section 2.2.16 Miscellaneous Note: All default settings are 0. 2.2.1 Network Media Connection Pin Name BGA Ball RXP[4:0] B10, B8, A7, B4, E7 178, 187, 190, 200, RXN[4:0] A10, C8, A6, B3,...

  • Page 22: Gmii/Mii Management

    ADM5120 Pin Name BGA Ball LED0[2:0] A14, E13, B14 Note: Registers, not hardware pins, control the LED display. There are 3 LEDs per port, and they can be programmed to any state, the programming information can be found in Table 2-1 below.

  • Page 23: Memory Bus

    ADM5120 Pin Name BGA Ball MII_0 Interface, if no need, let all pins be floated GCRS GCOL G_TXD[7:0]/G_TX F3, E1, G3, F2, F1, D[3:0] G2, J5, G1 G_TXE GTXC GRXC GRXDV GRXD[7:0]/RXD[3: L2, L1, K1, K2, L5, K3, K5, J2 2.2.5 Memory Bus...

  • Page 24: Sdram Control Signals

    ADM5120 Pin Name BGA Ball 2.2.6 SDRAM Control Signals Pin Name BGA Ball CLK_OUT SDRAM_CS0_N RAS_N CAS_N SDRAM_CS1_N DQM[3:0] T11, U12, T7, Y4 F_CS0_N F_CS1_N F_OE_N WE_N 2.2.7 UART Pin Name BGA Ball UDCD UDSR ADMtek Inc. PQFP Pin# PQFP Pin#...

  • Page 25: Jtag

    ADM5120 UCTS UDI0 UDO0 UDI1 UDO1 2.2.8 JTAG Pin Name BGA Ball TRST_N 2.2.9 General Purpose I/O (GPIO) Pin Name BGA Ball GPIO[7:0]/GPIO[3: E17, D18, C19, C20, E18, G17, D19, F18 LEDN[2:0] Refer to LED 2.2.10 PCI Pin Name BGA Ball...

  • Page 26: Usb

    ADM5120 Pin Name BGA Ball PCI_GNT[2:0] J19,J20,K20 PCI_IRDY PCI_PAR PCI_PERR PCI_REQ[2:0] K19,K18,J17 PCI_SER PCI_STOP PCI_TRDY PCI_INTA[2:0] L20,L19,K16 PCI_RESET PCI_CLK33 PCI_CLK33 2.2.11 USB Pin Name BGA Ball DMNS1 DPLS1 DMNS0 DPLS0 CLK48M 2.2.12 NAND Flash Pin Name BGA Ball NAND_OE_N NAND_WE_N 2.2.13 External CS/INT/wait...
  • Page 27 ADM5120 Pin Name BGA Ball CSX0# INTX0 CSX_1# INTX1# ADMtek Inc. PQFP Pin# Type Descriptions Interface Description if low, then wait until WAIT# go high External chip select, active low, available if en_csx_intx enable in the switch control register GPIO_config2...

  • Page 28: Power And Ground

    ADM5120 2.2.14 Power and Ground Pin Name BGA Ball F17, D13, D12, V14, V12, U10, T10, H3, H4, K17, DVDD J3, D14, D15, H17, W6, W11, U14, R17, M17, N4, P4 VDDA2 D4, A5, B5, A8, A9 VCCAD C5, B7, D11...

  • Page 29: Chapter 3 Function Description

    ADM5120 Chapter 3 Function Description System 3.1.1 Frequency The system clock frequency of ADM5120 is programmable as follows 00: 175MHz (Default) 01: 200MHz 1x: Reserved The number is set by the pull up or pull down of A[4:3]. This clock is for the MIPS, major switch cores, and SDRAM access.

  • Page 30: Phy

    ADM5120 3.2.1 PHY Overview The ADM5120 is an embedded 5 ports Ethernet PHY device. It is capable of operating at either 10Mbps or 100Mbps. The PHY is associated with the Physical Layer of the OSI model. The PHY performs functions between the Medium Dependent Interface (MDI) and the internal MAC of switch.

  • Page 31: Clock Recovery

    ADM5120 interference. The adaptive equalizer function conditions the incoming 100Base-T receive signal to compensate for this distortion. Transceivers that utilize an analog methodology to equalize are subject to system noise degrading their performance while a digital methodology provides better noise immunity but with the tradeoff of high power consumption.

  • Page 32: Switch Engine

    5. The packets from CPU 3.3.3 Routing When a packet comes from portA, ADM5120 will compare its destination MAC address with the MAC address in the MAC address lookup table. If the address is the same and port number is portA means that the packet is a local packet, then it is discarded. If the address is the same but port numbers are different, the packet is a unicast packet, and will be forwarded to the assigned port.

  • Page 33: Buffer Management

    ADM5120 does not do the flow control to CPU, mean – never send the flow control packets to CPU port, so the firmware needs to monitor the buffer status to prevent the packet lost.

  • Page 34: Vlan

    CPU traffic (mostly they are this bandwidth is charged.) 3.3.10 VLAN ADM5120 supports 7 port-grouping VLAN. Each of thr VLAN will be treated as the isolated ports. ADM5120 provides the VLAN MAC address function, if the packet is assigned with the VLAN address as its destination MAC address, then this packet will be forwarded to the CPU via DMA.

  • Page 35: Bandwidth Control Function

    64K- bit/ 128K /256K /512K/ 1M/ 4M/ 10M. In a fixed period, ADM5120 will count the per port RX and TX byte number, and compare with the bandwidth control threshold. If it is over this threshold, ADM5120 will turn on the proprietary scheme to control the RX/TX behavior.

  • Page 36: Receive Descriptors Content

    ADM5120 – Buffer1 has length information, if packet size is larger than buffer1 size, then get the rest of the data from buffer2. – Buffer address must be valid when a descriptor belongs to a switch, the switch engine will not check the address status.
  • Page 37 ADM5120 Control Own bit: • – If 0, the descriptor belongs to CPU. – If 1, the descriptor is released to WAN MAC or LAN SW, which means it can store the incoming packet based on the buffer address. If this is done, change the bit to 0.

  • Page 38: Usb 1.1 Host Controller

    ADM5120 USB 1.1 Host Controller 3.4.1 Block Diagram The following block diagram describes the functional blocks of the ADMtek USB 1.1 Host controller. Figure 3-1 Block Diagram of ADMtek USB 1.1 Host controller 3.4.2 System bus interface This block provides the USB Host controller with the connection to the AHB bus interface.

  • Page 39: Sie

    ADM5120 status. The operational register also provides the interface for the local host to transfer the data for control and interrupt endpoint. 3.4.4 SIE The SIE handles the link layer protocol of USB. It includes the following items Identify the USB SYNC field...

  • Page 40: Transfer Descriptor Format

    ADM5120 Description 31-27 Reserved 26-16 Maximum packet size The maximum data that can transmit/receive in one USB transaction. Format This bit indicates that this packet is for isochronous. 1: The data in this descriptor is for isochronous transfer. 0: The data in this descriptor is for general data transfer.
  • Page 41 ADM5120 DWORD 0 – Status Description OWNER Descriptor ownership bit – set to 0 when the host owns the descriptor, set to 1 by host to tell the USB Host controller owns the descriptor, the controller will clear this bit when reception has done.

  • Page 42: Dma Operation

    ADM5120 DWORD 1 – Data Buffer Pointer Description 31-0 Starting address of the data buffer This field indicates the starting address of the data buffer. Data buffer may be aligned on any byte. When an OUT or SETUP packet has been transmitted, this field will be updated as the next start address of the data buffer.

  • Page 43: Figure 3-2 Dma Operation In Host Mode

    ADM5120 If a USB zero length packet is received, then the received data length will be zero, and this buffer is retired due to short packet received. DM A Descr iptor Chain Head pkt A I SO (512B) USB bus SOF send by host ADMtek Inc.
  • Page 44 ADM5120 For Interrupt IN/OUT transactions, each ED just contains one valid TD. Since the Interrupt transaction is periodic, two parameters are defined in TD by software to guide hardware for doing Interrupt transfer, they are Frame Number and Interrupt service period.

  • Page 45: Figure 3-3 Interrupt In/Out Transactions

    ADM5120 Interrupt IN/OUT Transaction DMA Descriptor Chain Prior ED PKT A (32B) PKT C (16B) Current Frame Number ADMtek Inc. INT IN ED #1 INT OUT ED #2 MPS 64Byte MPS 32Byte TD Tail TD Tail TD Head TD Head ED descr.

  • Page 46: Chapter 4 Register Description

    ADM5120 Chapter 4 Register Description System Memory Map 0x2000 0000 0x1FC0 0000 0x12A0 0000 0x1280 0000 0x1260 0000 0x1240 0000 0x1220 0000 0x1200 0000 0x11C0 0000 0x11A0 0000 0x1160 0000 0x115f fff8 0x115f fff0 0x1150 0000 0x1140 0000 0x1120 0000...
  • Page 47 ADM5120 Memory mapping notes • There are two banks for SDRAM and Flash. • The two banks of SDRAM are the same size. control register, Base+1C, bit[2:0] • For SRAM SRAM_0, the bank0of NOR flash, boot flash – the address is fixed at 0x1FC0_0000 and the maximum size is 4M-byte.

  • Page 48: System And Interrupt Registers

    ADM5120 System and Interrupt Registers 4.2.1 Interrupt Control Register Map Offset Address Base + 00 Base + 04 Base + 08 Base + 0c Base + 10 Base + 14 Base + 18 Base + 1c Base + 20 Base + 24 Note: Base = 0x1220_0000 4.2.2.

  • Page 49: Irq_Raw_Status, Offset: 0X40

    ADM5120 4.2.4 IRQ_raw_status, offset: 0x40 Bits Type Name IRQ_raw_status[7 31:10 RO Reserved 4.2.5 IRQ_enable, offset: 0x80 Bits Type Name IRQ_enable[7:0] 31:10 RO Reserved 4.2.6 IRQ_enable_clear, offset: 0xc0 Bits Type Name IRQ_enable_clear [7:0] 31:10 Reserved 4.2.7 Reserved, offset: 0x10 Bits Type...

  • Page 50: Fiq_Status, Offset: 0X18

    ADM5120 4.2.9 FIQ_status, offset: 0x18 Bits Type Name FIQ_status[9:0] 31:10 Reserved 4.2.10 IRQ_test_source, offset: 0x1c Bits Type Name IRQ_test_source[9 31:10 Reserved 4.2.11 IRQ_source_sel, offset: 0x20 Bits Type Name IRQ_source_selec tion 31:1 Reserved 4.2.12 INT_level, offset: 0x24 Bits Type Name Reserved...

  • Page 51: Switch Control Register Map

    ADM5120 Switch Control Register Map Note: Base = 0x1200_0000 Description Code SftReset Reserved SWReset Global_St PHY_St Port_St Mem_cRWontrol SW_conf, offset: CPUp_conf Port_conf0 Port_conf1 Port_conf2 Reserved Reserved Reserved VLAN_GI VLAN_GII Send_trig Srch_cmd ADDR_st0 ADDR_st1 MAC_wt0 MAC_wt1 BW_cntl0 BW_cntl1 PHY_cntl0 PHY_cntl1 FC_th...

  • Page 52: Switch Control Register Description

    ADM5120 TOS_map1 Custom_pri1 Custom_pri2 Reserved Empty_cnt Port_cnt_sel Port_cnt Int_st Int_mask GPIO_conf0 GPIO_conf2 Watchdog0 Watchdog1 Swap_in Swap_out send_Hbaddr send_Lbaddr receive_Hbaddr receive_Lbaddr send_Hwaddr send_Lwaddr receive_Hwaddr Receive_Lwaddr Timer_int Timer Reserved Reserved port0_LED port1_LED port2_LED port3_LED port4_LED Note: Although some registers may be marked with a certain type, it may be possible that some bits in this register are different.

  • Page 53: Sftreset, Offset: 0X04

    ADM5120 19:16 Revision 21:20 Clock_spd NAND boot Dcache_Set Dcache_Size Icache_Set Icache_Size Package 31:30 Reserved 4.4.2 SftReset, offset: 0x04 Note: Whenever you write the register offset 0x04, the SftReset will be active. Bits Type Name SftReset 4.4.3 Boot_done, offset: 0x08 Bits...

  • Page 54: Phy_St, Offset: 0X14

    ADM5120 D_bist_fail L_bist_fail MC_bist_fail AT_bist_fail Dcache_D_test_fail Bit 5 and Bit 4 are respectively for the upper and lower Dcache_T_test_fail the memory of D-cache tag Icache_D_test_fail Bit 8 and Bit 7 are respectively for the upper and lower Icache_T_test_fail the memory of I-cache tag...

  • Page 55: Mem_Control, Offset: 0X1C

    ADM5120 4.4.8 Mem_control, offset: 0x1c Bits Type Name SDRAMsize Reserved SDRAM1_en Reserved 10:8 SRAM0_size 15:11 Reserved 18:16 RW SRAM1_size 28:19 Reserved CSX0_wt_hold_ext 31:30 Reserved 4.4.9 SW_conf, offset: 0x20 Bits Type Name Reserved Reserved age_tmr BC_prev ADMtek Inc. Description one bank information, the 2...
  • Page 56 ADM5120 Bits Type Name 11:10 RW Max_len Dis_colabt 14:13 RW Hash_alg force_bk 19:16 RW BP_num 21:20 RW BP_mode Rsrv_MC BISR_disable disMII_wasTX BISS_disable 27:26 RW BISS_TH ADMtek Inc. Description 00: disable, BC will be blocked, if 01=64 blocks 10=48 blocks 11=32 blocks...

  • Page 57: Cpup_Conf, Offset 0X24

    ADM5120 Bits Type Name 31:28 RW Req_lat 4.4.10 CPUp_conf, offset 0x24 Bits Type Name DisCPUport CRC_padding bridge mode Reserved 14:9 DisUN_port Reserved 21:16 RW DisMC_port 23:17 Reserved 29:24 RW DisBC_port 31:30 RW Reserved 4.4.11 Port_conf0, offset 0x28 Bits Type Name...

  • Page 58: Port_Conf1, Offset 0X2C

    ADM5120 4.4.12 Port_conf1, offset 0x2c Bits Type Name Dis_Learn 11:6 blocking_state 17:12 RW blocking_mode 19:18 Reserved 25:20 RW Port_age 31:26 RW SA_secured 4.4.13 Port_conf2, offset 0x30 Bits Type Name GMII_AN force_MIIport_spd force_MIIport_dpx force_MIIport_FC Force MII port 802.3x flow control ON if AN monitor ADMtek Inc.

  • Page 59: Reserved, Offset: 0X34

    ADM5120 Bits Type Name Reserved rev-MII TXC_check 10:9 Config_early_rdy[ 1:0] 15:11 Reserved 17:16 RW LED_flash_time 23:18 dis_uc_pause[5:0] Disable unicast pause frame. Default 00000. 31:24 Reserved 4.4.14 Reserved, offset: 0x34 Bits Type Name Reserved 4.4.15 Reserved, offset: 0x38 Bits Type Name Reserved ADMtek Inc.

  • Page 60: Reserved, Offset: 0X3C

    ADM5120 4.4.16 Reserved, offset: 0x3c Bits Type Name Reserved 4.4.17 VLAN_GI, offset 0x40 Bits Type Name VLAN0 Reserved 14:8 VLAN1 Reserved 22:16 RW VLAN2 Reserved 30:24 RW VLAN3 Reserved 4.4.18 VLAN_GII, offset 0x44 Bits Type Name VLAN4 Reserved 14:8 VLAN5...

  • Page 61: Addr_St0, Offset 0X50

    ADM5120 4.4.21 ADDR_st0, offset 0x50 Bits Type Name Data_rdy Table_end filter VLAN VLAN_en 12:7 P_number 15:13 RO age_field 31:16 RO MAC_srch0 4.4.22 ADDR_st1, offset 0x54 Bits Type Name 31:0 MAC_srch1 4.4.23 MAC_wt0, offset 0x58 Bits Type Name wtMAC_cmd wtMAC_done wtfilter...

  • Page 62: Bw_Cntl0, Offset 0X60

    ADM5120 4.4.25 BW_cntl0, offset 0x60 Bits Type Name P0tx_bwcntl Reserved P0rx_bwcntl Reserved 10:8 P1tx_bwcntl Reserved 14:12 RW P1rx_bwcntl Reserved 18:16 RW P2tx_bwcntl Reserved 22:20 RW P2rx_bwcntl Reserved 26:24 RW P3tx_bwcntl Reserved 30:28 RW P3rx_bwcntl Reserved 4.4.26 BW_cntl1, offset 0x64 Bits...

  • Page 63: Phy_Cntl1, Offset 0X6C

    ADM5120 RD_cmd Reserved 31:16 RW WT_data 4.4.28 PHY_cntl1, offset 0x6c Bits Type Name WT_done RD_rdy 15:2 Reserved 31:16 RO RD_data 4.4.29 FC_th, offset 0x70 Bits Type Name Drop2_set 15:8 Drop2_rls 24:16 RW FC_set 31:25 Reserved Note: The working global thresholds = (register value) * 2, The Drop1_set[7:0] threshold default value = 137 blocks, The default working Drop1_set threshold = 137 x 2 =274.

  • Page 64: Phy_Cntl3, Offset 0X80

    ADM5120 19:15 RW fc_rec 24:20 RW PHY reset 29:25 RW Auto MDIX Rec_mcc_average Per port PHY auto MDIX enable Reserved 4.4.33 PHY_cntl3, offset 0x80 Bits Type Name Rec_bslimit FILTSEL ISHSEL IINSEL APOLDIS ENRJAB DISJAB FGDLINK 13:12 RW LFAILTM INTCHKEN CBDETEN...

  • Page 65: Tos_En, Offset 0X8C

    ADM5120 Reserved 10:8 VLAN_th 31:11 Reserved 4.4.36 TOS_en, offset 0x8c Bits Type Name TOS_pri 31:6 Reserved 4.4.37 TOS_map0, offset 0x90 Bits Type Name 31:0 TOS_map0 4.4.38 TOS_map1, offset 0x94 Bits Type Name 31:0 TOS_map1 4.4.39 Custom_pri1, offset 0x98 Bits Type...

  • Page 66: Phy_Cntl4, Offset 0Xa0

    ADM5120 31:24 Reserved 4.4.41 PHY_cntl4, offset 0xA0 Bits Type Name P0_cbbrk_length Port 0 cable broken length P0_cbbrk Reserved P1_cbbrk_length Port 1 cable broken length P1_cbbrk Reserved P2_cbbrk_length Port 2 cable broken length P2_cbbrk Reserved 13:12 RO P3_cbbrk_length Port 3 cable broken length...

  • Page 67: Int_St, Offset 0Xb0

    ADM5120 sel_info 4.4.45 Int_st, offset 0xB0 Note: All bits are “write 1 clear” Bits Type Name send_H_done send_L_done rx_H_done rx_L_done H_Descriptor_full The descriptor, “high priority receive”, are full L_Descriptor_ful the descriptor, “normal priority receive”, are full port0_que_full port1_que_full port2_que_full port3_que_full...

  • Page 68: Int_Mask, Offset 0Xb4

    ADM5120 BC_storm Reserved Port_status_chg Intruder Watchdog0_tmr_expir Watchdog1_tmr_expir rx_desc_err send_desc_err CPU_hold 31:25 Reserved 4.4.46 Int_mask, offset 0xB4 Note: 1: mask the interrupt Bits Type Name M_send_H_done M_send_L_done M_rx_H_done M_rx_L_done M_H_Descriptor_full M_L_Descriptor_full M_port0_que_full M_port1_que_full M_port2_que_full M_port3_que_full M_port4_que_full M_port5_que_full Reserved M_CPU_que_full M_Global_que_full M_Must_drop...

  • Page 69: Gpio_Conf0, Offset 0Xb8

    ADM5120 4.4.47 GPIO_conf0, offset 0xB8 Bits Type Name in_out0 15:8 in_value0 23:16 RW out_en0 31:24 RW out_value0 4.4.48 GPIO_conf2, offset 0xBc Bits Type Name Reserved en_csx_intx en_csx1_intx1 en_wait 31:7 Reserved 4.4.49 Watchdog0, offset 0xC0 Bits Type Name 14:0 Watchdog0_tmr Reserved...

  • Page 70: Swap_In, Offset 0Xc8

    ADM5120 30:16 RW Watchdog1_tmr_s Watchdog1_drop_ 4.4.51 Swap_in, offset 0xC8 Bits Type Name Swap_din 15:8 Swap_din 23:16 RW Swap_din 31:24 Swap_din 4.4.52 Swap_out, offset 0xCc Bits Type Name Swap_dout 15:8 Swap_dout 23:16 RO Swap_dout 31:24 RO Swap_dout 4.4.53 send_Hbaddr, offset 0xD0...

  • Page 71: Receive_Lbaddr, Offset 0Xdc

    ADM5120 31:25 Reserved 4.4.56 receive_Lbaddr, offset 0xDc Bits Type Name 24:0 receive_LBaddr 31:25 Reserved 4.4.57 send_Hwaddr, offset 0xE0 Bits Type Name 24:0 send_HWaddr 31:25 Reserved 4.4.58 send_Lwaddr, offset 0xE4 Bits Type Name 24:0 port_sel 31:25 Reserved 4.4.59 receive_Hwaddr, offset 0xE8...

  • Page 72: Timer, Offset 0Xf4

    ADM5120 4.4.62 Timer, offset 0xF4 Bits Type Name 15:0 timer timer_en 31:17 Reserved 4.4.63 Reserved, offset 0xF8 Bits Type Name 31:0 Reserved 4.4.64 Reserved, offset 0xFc Bits Type Name 31:0 Reserved 4.4.65 port0_LED, offset 0x100 Bits Type Name p0_LED0 p0_LED1...

  • Page 73: Port3_Led, Offset 0X10C

    ADM5120 31:15 Reserved Note: port2 LED[2:0] pin (147,158,160) configuration register 4.4.68 port3_LED, offset 0x10c Bits Type Name P3_LED0 P3_LED1 11:8 P3_LED2 14:12 RO GPIOL_in[11:9] 31:15 Reserved Note: port3 LED[2:0] pin (144,145,146) configuration register 4.4.69 port4_LED, offset 0x110 Bits Type Name...

  • Page 74: Usb Control Status Registers Description

    ADM5120 USB Control Status Registers Description Host processors can only access USB 1.1 host/device controller registers with double word (32 bits) reads or writes on double word boundaries. 4.6.1 General Control , offset 0x00 Bits Type Name R/W HOST_EN R/W SW_INT_REQ...

  • Page 75: Interrupt Enable, Offset 0X08

    ADM5120 Bits Type Name R/W1 R/W1 19:12 R/W1 Reserved R/W1 TD_Complete 25:21 R/W1 Reserved 28:26 RO Reserved R/W1 SW_INT R/W1 FATAL_INT RO INT_ACT 4.6.3 Interrupt Enable, offset 0x08 Bits Type Name 30:0 INT_MASK INT_EN 4.6.4 Reserved, offset 0x0C Bits Type Name ADMtek Inc.

  • Page 76: Host General Control, Offset 0X10

    ADM5120 31:0 Reserved 4.6.5 Host General Control, offset 0x10 Bits Type Name R/W BUS_STATE R/W DMA_EN 31:3 RO Reserved 4.6.6 Reserved, offset 0x14 Bits Type Name 31:0 Reserved 4.6.7 SOF Frame interval, offset 0x18 Bits Type Name 13:0 R/W FM_INTERVAL Frame interval...

  • Page 77: Sof Frame Number, Offset 0X1C

    ADM5120 4.6.8 SOF Frame number, offset 0x1C Bits Type Name 15:0 R/W FM_NUM 29:16 R/W FM_REMAININ RO Reserved R/W FM_REMAININ G_TOG 4.6.9 Reserved, offset 0x20 – 0x6C Bits Type Name 31:0 Reserved 4.6.10 Low speed threshold, offset 0x70 Bits Type Name...

  • Page 78: Rh Descriptor, Offset 0X74

    ADM5120 4.6.11 RH descriptor, offset 0x74 Bits Type Name RO NUM_PORT R/W PSM R/W NPS R/W OCPM R/W NOCP 15:12 RO Reserved 23:16 R/W PPCM ADMtek Inc. Description Power Switch Mode This bit is used to specify how the power switching of the Root Hub ports is controlled.
  • Page 79 ADM5120 Bits Type Name R/W LPS R/W OCI R/W LPSC R/W OCIC R/W DRWE R/W CRWE 31:30 RO Reserved ADMtek Inc. Description is configured to global switching mode (PSM =0), this field is not valid. bit 0: Reserv ed bit 1: Ganged-power mask on Port #1...

  • Page 80: Port X Status, Offset 0X78

    ADM5120 4.6.12 Port x status, offset 0x78 Bits Type Name R/W CCS R/W PES R/W PSS ADMtek Inc. Description Current connect status (read)This bit reflects the current state of the downstream port. 0 = no device connected 1 = device connected (write)ClearPortEnable The HCD writes a 1 to this bit to clear the PES.
  • Page 81 ADM5120 Bits Type Name R/W POCI R/W PRS RO Reserved R/W PPS ADMtek Inc. Description this write does not set PSS; instead it sets CSC. This informs the driver that it attempted to suspend a disconnected port. (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis.
  • Page 82 ADM5120 Bits Type Name R/W LSDV 15:10 RO Reserved R/W CSC R/W PESC R/W PSSC ADMtek Inc. Description 0 = port power is off 1 = port power is on (write) SetPortPower The HCD writes a 1 to set the PPS bit. Writing a 0 has no effect.

  • Page 83: Host Descriptor Head Starting Address, Offset 0X80

    ADM5120 Bits Type Name R/W OCIC R/W PRSC 31:21 RO Reserved 4.6.13 Host Descriptor Head Starting Address, offset 0x80 Bits Type Name Reserved 31:4 DSC_ADDR MPMC Registers 4.7.1 MPMC Registers Summary Offset 000h 004h 008h 020h 024h 030h 034h 038h...
  • Page 84 ADM5120 Offset 044h 048h 04Ch 050h 054h 058h 080h 100h, 120h, 140h, 160h 104h, 124h, 144h, 164h 200h, 220h, 240h, 260h 204h, 224h, 244h, 264h 208h, 228h, 248h, 268h 20Ch, 22Ch, 24Ch, 26Ch 210h, 230h, 250h, 270h 214h, 234h, 254h, 274h...

  • Page 85: Mpmc Control Register, Offset 000H

    ADM5120 Offset FF4h FF8h FFCh 4.7.2 MPMC Control register, offset 000h Bit # Type Name 31:4 Reserved 4.7.3 MPMC Status register, offset 004h Bit # Type Name ADMtek Inc. Register MPMCPCellID0 MPMCPCellID1 MPMCPCellID2 MPMCPCellID3 Descriptions MPMC Enable: indicates if the PrimeCell MPMC is enabled or disabled.

  • Page 86: Mpmc Config Register, Offset 008H

    ADM5120 Bit # Type Name SREFACKA 31:3 Reserved 4.7.4 MPMC Config register, offset 008h Bit # Type Name Reserved 31:9 Reserved 4.7.5 MPMC Dynamic Control register, offset 020h Bit # Type Name ADMtek Inc. Descriptions memory controller enters the low-power or disabled...

  • Page 87: Mpmc Dynamic Refresh Register, Offset 024H

    ADM5120 Bit # Type Name MPMCSREFREQ (SR) Reserved 12:9 Reserved 31:14 Reserved 4.7.6 MPMC Dynamic Refresh register, offset 024h Bit # Type Name 10:0 REFRESH 3:11 Reserved 4.7.7 MPMC Dynamic RP register, offset 030h Bit # Type Name 31:4 Reserved Note: The delay is in MPMCCLK cycles.

  • Page 88: Mpmc Dynamic Ras Register, Offset 034H

    ADM5120 4.7.8 MPMC Dynamic RAS register, offset 034h Bit # Type Name R/W tRAS 31:4 Reserved Note: The delay is in MPMCCLK cycles. 4.7.9 MPMC Dynamic SREX register, offset 038h Bit # Type Name tSREX 31:4 Reserved Note: The delay is in MPMCCLK cycles.

  • Page 89: Mpmc Dynamic Rc Register, Offset 048H

    ADM5120 4.7.13 MPMC Dynamic RC register, offset 048h Bit # Type Name 31:5 Reserved Note: The delay is in MPMCCLK cycles. 4.7.14 MPMC Dynamic RFC register, offset 04Ch Bit # Type Name tRFC 31:5 Reserved Note: The delay is in MPMCCLK cycles.

  • Page 90: Mpmc Static Extended Wait Register, Offset 080H

    ADM5120 Bit # Type Name 31:4 Reserved Note: The delay is in MPMCCLK cycles. 4.7.18 MPMC Static Extended Wait register, offset 080h Bit # Type Name EXTENDEDWAIT External wait time out: 31:10 Reserved Note: The delay is in HCLK cycles.

  • Page 91: Table 4-2 Address Map

    ADM5120 Bit # Type Name Reserved Reserved 29:28 R/W 31:30 Reserved ADMtek Inc. Descriptions 101 = 11-bit 110 = reserved 111 = reserved Read undefined, must be written as zeros. Number of banks: 0 = two banks (reset value on nPOR) 1 = four banks.
  • Page 92 ADM5120 Register Description ADMtek Inc. 4-45...

  • Page 93: Mpmc Dynamic Ras Cas[0,1,2,3] Register

    ADM5120 4.7.20 MPMC Dynamic Ras Cas[0,1,2,3] register Note: offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2 respectively Bit # Type Name Reserved 31:10 Reserved Note: The RAS to CAS latency (RAS) and CAS latency (CAS) are both defined in MPMCCLK cycles.

  • Page 94: Mpmc Static Wait Wen [0,1,2,3] Register

    ADM5120 Bit # Type Name 18:9 Reserved 31:21 Reserved Note: Synchronous burst mode memory devices are not supported. 4.7.22 MPMC Static Wait Wen [0,1,2,3] register Note: offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2 respectively Bit #...

  • Page 95: Mpmc Static Wait Rd [0,1,2,3] Register

    ADM5120 Note: The delay is WAITOEN x tHCLK. 4.7.24 MPMC Static Wait Rd [0,1,2,3] register Note: offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2 respectively Bit # Type Name WAITRD 31:5 Reserved Note: For non-sequential reads, the wait state time is (WAITRD+1) x tHCLK.

  • Page 96: Mpmc Static Wait Turn [0,1,2,3] Register

    ADM5120 Bit # Type Name 31:5 Reserved Note: The wait state time for write accesses after the first read is WAITWR x tHCLK. 4.7.27 MPMC Static Wait Turn [0,1,2,3] register Note: offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2...

  • Page 97: Mpmc Periphid5-7 Register, Offset Fd4H, Fd8H, Fdch

    ADM5120 4.7.30 MPMC PeriphID5-7 register, offset FD4h, FD8h, FDCh Bit # Type Name 31:0 Reserved 4.7.31 Conceptual MPMC Peripheral ID register Bit # Type Name 11:0 Part number 19:12 R Designer 23:20 R Revision 31:24 R Configuration Note: The four eight-bit peripheral identification registers are described in the following sections: MPMCPeriphID0 register MPMCPeriphID1 registers on next page.

  • Page 98: Mpmc Periphid3 Register, Offset Fech

    ADM5120 4.7.35 MPMC PeriphID3 register, offset FECh Bit # Type Name Configuration Configuration Configuration Configuration 31:8 Reserved Note: The MPMCPeriphID2 register is hard-coded and the fields within the register determine the reset value. 4.7.36 MPMC PrimeCellID register, offset 00h Bit #...

  • Page 99: Mpmc Pcellid1 Register, Offset Ff4H

    ADM5120 4.7.38 MPMC PCellID1 register, offset FF4h Bit # Type Name 31:8 Reserved 4.7.39 MPMCPCellID2 register, offset FF8h Bit # Type Name 31:8 Reserved 4.7.40 MPMCPCellID3 register, offset FFCh Bit # Type Name 31:8 Reserved UART Registers 4.8.1 Remap and Pause Controller Registers...

  • Page 100: Uart Receive Status Register/Error Clear Register, Offset 04H

    ADM5120 4.8.3 UART receive status register/error clear register, offset 04h Bit # Type Name Reserved 4.8.4 UART line control register, high byte, offset 08h Bit # Type Name ADMtek Inc. Descriptions Framing Error (FE): When this bit is set to 1, it indicates that the received character did not have a valid stop bit.

  • Page 101: Uart Line Control Register, Middle Byte, Offset 0Ch

    ADM5120 Bit # Type Name STP2 WLEN Reserved 4.8.5 UART line control register, middle byte, offset 0ch Bit # Type Name BAUD DIVMS 4.8.6 UART line control register, low byte, offset 10h Bit # Type Name BAUD DIVLS Note: The baud rate divisor is calculated as follow:...

  • Page 102: Uart Flag Register (Uartfr), Offset 18H

    ADM5120 Bit # Type Name RTIE Reserved 4.8.8 UART flag register (UARTFR), offset 18h Bit # Type Name ADMtek Inc. Descriptions Modem status change when one of the following events occurs: (1) 0 → 1 (2) 1 → 0 Receive interrupt enable: If this bit is set to 1, the receive interrupt is enabled.
  • Page 103 ADM5120 Bit # Type Name BUSY RXFE TXFF RXFF TXFE ADMtek Inc. Descriptions (nUARTDSR) modem status input. That is , the bit is 1 when the modem status input is 0. This bit is the complement of the UART data carrier detect (nUARTDCD) modem status input.

  • Page 104: Uartiir/Uarticr, Offset 1Ch

    ADM5120 4.8.9 UARTIIR/UARTICR, offset 1ch Bit # Type Name RTIS Reserved UARTICR ADMtek Inc. Descriptions This bit is set to 1 if the UARTRTINTR modem status interrupt is asserted. This bit is set to 1 if the UARTRTINTR receive interrupt is asserted.

  • Page 105: Dc Specifications

    ADM5120 Chapter 5 Electrical Specification Absolute Maximum Ratings Supply Voltage (Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection DC Specifications Parameter Description Supply Voltage Supply Voltage (I / O) Power Supply Power Supply (I / O) Input LOW Voltage...

  • Page 106: Ac Timing

    ADM5120 5.3 AC Timing 5.3.1 SDRAM interface (Unit: ns, Min: best case, Max: worst case) Signal Name clock cycle time command/address setup delay time in precharge stage command/address hold delay time in precharge stage command/address setup delay time in active stage...

  • Page 107: Figure 5-2 Active Command

    ADM5120 Active Com m and SCLK SDC_CSZ[0] SDC_RASZ SDC_CASZ SDC_W EZ XA[14:0] ADMtek Inc. addr Figure 5-2 Active Command Electrical Specification Tas Tah...

  • Page 108: Figure 5-3 Write Command

    ADM5120 W rite Com m and SCLK SDC_CSZ[0] SDC_RASZ SDC_CASZ SDC_W EZ SDC_DQM[3:0] XA[14:0] XD[31:0] Read Command SCLK SDC_CSZ[0] SDC_RASZ SDC_CASZ SDC_W EZ SDC_DQM[3:0] XA[14:0] XD[31:0] ADMtek Inc. 4'b0000 addr data1 data2 data3 data4 Figure 5-3 Write Command 4'b0000 addr...

  • Page 109: Memory Bus Read Timing

    ADM5120 5.3.2 Memory Bus Read Timing ROM/FLASH/External Memory: Two wait state Read Timing CLK_OUT ADDR[19:0] DATA[31:0] F_CSX_N F_OE_N ROM/FLASH/External Memory: Two Output enable delay state Read Timing CLK_OUT ADDR[19:0] DATA[31:0] F_CSX_N F_OE_N Notes: T is the period of CLK_OUT (11.5ns/87.5Mhz)

  • Page 110: Memory Bus Write Timing

    ADM5120 5.3.3 Memory Bus Write Timing ROM/FLASH/External Memory: Zero Wait state Timing CLK_OUT ADDR[19:0] DATA[31:0] F_CSX_N WE_N ROM/FLASH/External Memory: Two Wait state WriteTiming CLK_OUT ADDR[19:0] DATA[31:0] F_CSX_N WE_N ROM/FLASH/External Memory: Two Write enable delay state WriteTiming CLK_OUT ADDR[19:0] DATA[31:0] F_CSX_N WE_N Notes: T is the period of CLK_OUT (11.5ns/87.5Mhz)

  • Page 111: Chapter 6 Packaging

    ADM5120 Chapter 6 Packaging Ball Grid Array (BGA) 324-pin Note: Scale = mm ADMtek Inc. Packaging...

  • Page 112: Plastic Quad Flat Pack (Pqfp) 208-Pin

    ADM5120 Plastic Quad Flat Pack (PQFP) 208-pin Note: Scale = mm Symbol MIN. 0.17 ADMtek Inc. MILLIMETER NOM. MAX. MIN. 0.20 0.27 0.007 0.50 BSC. 25.50 25.50 0.25 0.20 0.08 Packaging INCH NOM. 0.008 0.011 0.020 BSC. 1.004 1.004 0.010 0.008...

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