Sftreset, Offset: 0X04; Note: Whenever You Write The Register Offset 0X04, The Sftreset Will Be Active; Boot_Done, Offset: 0X08; Swreset, Offset: 0X0C - ADMtek ADM5120 Datasheet

ADM5120
19:16 Revision
21:20 Clock_spd
24 NAND boot
25 Dcache_Set
26 Dcache_Size
27 Icache_Set
28 Icache_Size
29 Package
31:30 Reserved

4.4.2 SftReset, offset: 0x04

Note: Whenever you write the register offset 0x04, the SftReset will be active.

Bits Type Name
WO SftReset

4.4.3 Boot_done, offset: 0x08

Bits Type Name
0 RW Reserved

4.4.3 SWReset, offset: 0x0c

Note: Whenever you write the register offset 0x04, the SWReset will be active.
Bits Type Name
WO SWReset

4.4.5 Global_St, offset: 0x10

Bits Type Name
ADMtek Inc.
Revision code = 1000 (5120)
The PLL setting:
00: 175MHz (Default)
01: 200MHz
1x: Reserved
Configured in the NAND flash boot
1: 2K per way. 0: 4K per way
1: 2 Ways. 0: 1 Way.
1: 2K per way. 0: 4K per way
1: 2 Ways. 0: 1 Way.
0: BGA. 1: 208PQFP/disable GMII
Not Applicable
Description
Do Software reset when write, reset all logic, PHY and
memory, and down load the NAND flash content again.
Same as hardware reset.
Description
1: the software boot process is done and the address
table can return to switch controller
Description
Do SW reset when write, including SW engine, data-
buffer, link table, and PHY excluding address table.
(Recommend stop PHY before reset switch)
Description
Register Description
00
Initial value
Initial value
Initial value
Initial value
4-6