Port X Status, Offset 0X78 - ADMtek ADM5120 Datasheet

ADM5120

4.6.12 Port x status, offset 0x78

Bits Type Name
0 R/W CCS
1 R/W PES
2 R/W PSS
ADMtek Inc.
Description
Current connect status
(read)This bit reflects the current state of the
downstream port.
0 = no device connected
1 = device connected
(write)ClearPortEnable
The HCD writes a 1 to this bit to clear the PES.
Writing a 0 has no effect. The CCS is not
affected by any write.
Note: This bit is always read 1 when the attached device
is nonremovable
(read) PortEnableStatus
This bit indicates whether the port is enabled or
disabled. The Root Hub may clear this bit when an
overcurrent condition, disconnect event, switched-off
power, or operational bus error such as babble is
detected. This change also causes PESC to be set. HCD
sets this bit by writing SPE and clears it
by writing CPE. This bit cannot be set when
CCS is cleared. This bit is also set, if not already, at the
completion of a port reset when RSC is set or port
suspend when SSC is set.
0 = port is disabled
1 = port is enabled
(write) SetPortEnable
The HCD sets PortEnableStatus by writing a 1. Writing
a 0 has no effect. If CCS is cleared, this write does not
set PES, but instead sets CSC.
This informs the driver that it attempted to enable a
disconnected port.
(read)PortSuspendStatus
This bit indicates the port is suspended or in the resume
sequence.
It is set by a SSS write and cleared when PSSC is set at
the end of the resume interval. This bit cannot be set if
CCS is cleared. This bit is also cleared when PRSC is
set at the end of the port reset or when the HC is placed
in the USBRESUME state. If an upstream resume is in
progress, it should propagate to the HC.
0 = port is not suspended
1 = port is suspended
(write) SetPortSuspend
The HCD sets the PSS bit by writing a 1 to this bit.
Writing a 0 has no effect. If CCS is cleared,
Register Description
Initial value
0
0
0
4-33