System And Interrupt Registers; Interrupt Control Register Map; Interrupt Request Source Description; Irq_Status, Offset: 0X00 - ADMtek ADM5120 Datasheet

ADM5120
4.2

System and Interrupt Registers

4.2.1 Interrupt Control Register Map

Offset Address
Base + 00
Base + 04
Base + 08
Base + 0c
Base + 10
Base + 14
Base + 18
Base + 1c
Base + 20
Base + 24
Note: Base = 0x1220_0000

4.2.2. Interrupt Request Source Description

Bit
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Note: Only support level sensitive interrupts.
The external interrupt level, active high or low can be programmed

4.2.3 IRQ_status, offset: 0x00

Bits Type Name
9:0 RO IRQ_status[7:0]
31:10 RO Reserved
ADMtek Inc.
name
IRQ_status
IRQ_raw_status
IRQ_enable
IRQ_enable_clear
Reserved
INT_mode
FIQ_status
IRQ_test_source
IRQ_source_sel
INT_level
Name Description
Sw_int Switch interrupt, refer to B+B0, B+B4
PCI 2 PCI INT2
PCI 1 PCI INT1
PCI 0 PCI INT0
Intx_1 Internal interrupt 1, refer to GPIO[4] is the source
Intx_0 Internal interrupt 0, refer to GPIO[2] is the source
USB USB interrupt source
UART1 UART1 interrupt source
UART0 UART0 interrupt source
timer Timer interrupt, refer to B+F0 and B+F4
Description
The status of the interrupt sources after
masking.
1: the corresponding IRQ is active, and
generate the interrupt to MIPS
Register Description
Initial value
0
0
4-1