ADMtek ADM5120 Manuals

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ADMtek ADM5120 Datasheet

ADMtek ADM5120 Datasheet (112 pages)

Home Gateway Controller

Brand: ADMtek | Category: Gateway | Size: 4 MB

Table of Contents

Revision History
3
Table of Contents
4
Chapter 1 Product Overview

11
- Overview
  11
  - Product Order Information
    11
- Features
  12
- Block Diagram
  14
- Abbreviations
  14
- Figure 1-1 ADM5120 Block Diagram
  14
- Conventions
  16
  - Data Lengths
    16
  - Register Descriptions
    16
  - Pin Descriptions
    16
Chapter 2 Interface Description

17
- Pin Assignment
  17
- Pin Description by Function
  20
  - Network Media Connection
    21
  - Clock for Network
    21
  - Led
    21
  - GMII/MII Management
    22
  - Table 2-3 LED Program Table
    22
  - Memory Bus
    23
  - SDRAM Control Signals
    24
  - Uart
    24
  - Jtag
    25
  - General Purpose I/O (GPIO)
    25
  - Pci
    25
  - Usb
    26
  - NAND Flash
    26
  - External Cs/Int/Wait
    26
  - Power and Ground
    28
  - Regulator Interface
    28
  - Miscellaneous
    28
Chapter 3 Function Description

29
- System
  29
  - Frequency
    29
  - Boot Code Data-Width
    29
  - GMII/MII Port
    29
- Phy
  30
  - PHY Overview
    30
  - Link Detect
    30
  - Auto-Negotiation
    30
  - Digital Adaptive Equalizer
    30
  - Clock Recovery
    31
  - Admtek Inc
    31
  - Stream Cipher Scrambler/ De-Scrambler
    31
  - Encoder/Decoder
    31
- Switch Engine
  32
  - Hashing Function
    32
  - Learning Process
    32
  - Routing
    32
  - Forwarding
    32
  - Buffer Management
    33
  - Flow Control (Patent Pending)
    33
  - Full Duplex
    33
  - Half Duplex
    33
  - Packet Priority and Class of Service (Cos)
    33
  - Vlan
    34
  - Address Table Access
    34
  - Address Security
    34
  - Bandwidth Control Function
    35
  - Send Descriptors Content
    35
  - Receive Descriptors Content
    36
- Usb 1.1 Host Controller
  38
  - Block Diagram
    38
  - System Bus Interface
    38
  - Operational Register
    38
  - Figure 3-1 Block Diagram of Admtek USB 1.1 Host Controller
    38
  - Sie
    39
  - Dpll
    39
  - Memory bist
    39
- Dma Operation
  39
Chapter 4 Register Description

46
- System Memory Map
  46
- Figure 4-1 System Memory Map
  46
- System and Interrupt Registers
  48
  - Interrupt Control Register Map
    48
  - Interrupt Request Source Description
    48
  - Irq_Status, Offset: 0X00
    48
  - Chapter 4 Register Description
    48
  - Irq_Raw_Status, Offset: 0X40
    49
  - Irq_Enable, Offset: 0X80
    49
  - Irq_Enable_Clear, Offset: 0Xc0
    49
  - Reserved, Offset: 0X10
    49
  - Int_Mode, Offset: 0X14
    49
  - Fiq_Status, Offset: 0X18
    50
  - Irq_Test_Source, Offset: 0X1C
    50
  - Irq_Source_Sel, Offset: 0X20
    50
  - Int_Level, Offset: 0X24
    50
- Switch Control Register Map
  51
- Switch Control Register Description
  52
- Admtek Inc
  52
  - Code, Offset: 0X00
    52
  - Sftreset, Offset: 0X04
    53
  - Note: Whenever You Write the Register Offset 0X04, the Sftreset will be Active
    53
  - Boot_Done, Offset: 0X08
    53
  - Swreset, Offset: 0X0C
    53
  - Global_St, Offset: 0X10
    53
  - Phy_St, Offset: 0X14
    54
  - Port_St, Offset: 0X18
    54
  - Mem_Control, Offset: 0X1C
    55
  - Sw_Conf, Offset: 0X20
    55
  - Cpup_Conf, Offset 0X24
    57
  - Port_Conf0, Offset 0X28
    57
  - Port_Conf1, Offset 0X2C
    58
  - Port_Conf2, Offset 0X30
    58
  - Reserved, Offset: 0X34
    59
  - Reserved, Offset: 0X38
    59
  - Reserved, Offset: 0X3C
    60
  - VLAN_GI, Offset 0X40
    60
  - VLAN_GII, Offset 0X44
    60
  - Send_Trig, Offset 0X48
    60
  - Srch_Cmd, Offset 0X4C
    60
  - Addr_St0, Offset 0X50
    61
  - Addr_St1, Offset 0X54
    61
  - Mac_Wt0, Offset 0X58
    61
  - Mac_Wt1, Offset 0X5C
    61
  - Bw_Cntl0, Offset 0X60
    62
  - Bw_Cntl1, Offset 0X64
    62
  - Phy_Cntl0, Offset 0X68
    62
  - Phy_Cntl1, Offset 0X6C
    63
  - Fc_Th, Offset 0X70
    63
  - Adj_Port_Th, Offset 0X74
    63
  - Port_Th, Offset 0X78
    63
  - Phy_Cntl2, Offset 0X7C
    63
  - Phy_Cntl3, Offset 0X80
    64
  - Pri_Cntl, Offset 0X84
    64
  - Vlan_Pri, Offset 0X88
    64
  - Tos_En, Offset 0X8C
    65
  - Tos_Map0, Offset 0X90
    65
  - Tos_Map1, Offset 0X94
    65
  - Custom_Pri1, Offset 0X98
    65
  - Custom_Pri2, Offset 0X9C
    65
  - Phy_Cntl4, Offset 0Xa0
    66
  - Empty_Cnt, Offset 0Xa4
    66
  - Port_Cnt_Sel, Offset 0Xa8
    66
  - Port_Cnt, Offset 0Xac
    66
  - Int_St, Offset 0Xb0
    67
  - Admtek Inc
    67
  - Int_Mask, Offset 0Xb4
    68
  - Gpio_Conf0, Offset 0Xb8
    69
  - Gpio_Conf2, Offset 0Xbc
    69
  - Watchdog0, Offset 0Xc0
    69
  - Watchdog1, Offset 0Xc4
    69
  - Swap_In, Offset 0Xc8
    70
  - Swap_Out, Offset 0Xcc
    70
  - Send_Hbaddr, Offset 0Xd0
    70
  - Send_Lbaddr, Offset 0Xd4
    70
  - Receive_Hbaddr, Offset 0Xd8
    70
  - Receive_Lbaddr, Offset 0Xdc
    71
  - Send_Hwaddr, Offset 0Xe0
    71
  - Send_Lwaddr, Offset 0Xe4
    71
  - Receive_Hwaddr, Offset 0Xe8
    71
  - Receive_Lwaddr, Offset 0Xec
    71
  - Timer_Int, Offset 0Xf0
    71
  - Timer, Offset 0Xf4
    72
  - Reserved, Offset 0Xf8
    72
  - Reserved, Offset 0Xfc
    72
  - Port0_Led, Offset 0X100
    72
  - Port1_Led, Offset 0X104
    72
  - Port2_Led, Offset 0X108
    72
  - Port3_Led, Offset 0X10C
    73
  - Port4_Led, Offset 0X110
    73
- Usb Control Status Register Map
  73
- Usb Control Status Registers Description
  74
- Mpmc Registers
  83
- Uart Registers
  99
- DC Specifications
  105
- A Bsolute M Aximum R Atings
  105
Chapter 5 Electrical Specification

105
- Ac Timing
  106
  - SDRAM Interface
    106
  - Figure 5-1 Precharge Command
    106
  - Figure 5-2 Active Command
    107
  - Figure 5-3 Write Command
    108
  - Figure 5-4 Read Command
    108
  - Electrical Specification
    108
  - Memory Bus Read Timing
    109
  - Memory Bus Write Timing
    110
Chapter 6 Packaging

111
- Ball Grid Array (BGA) 324-Pin
  111
- Plastic Quad Flat Pack (PQFP) 208-Pin
  112

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