Int_St, Offset 0Xb0; Adm5120; Admtek Inc - ADMtek ADM5120 Datasheet

ADM5120

RO sel_info

4.4.45 Int_st, offset 0xB0

Note: All bits are "write 1 clear"
Bits Type Name
0 RW send_H_done
1 RW send_L_done
2 RW rx_H_done
3 RW rx_L_done
4 RW H_Descriptor_full The descriptor, "high priority receive", are full
5 RW L_Descriptor_ful the descriptor, "normal priority receive", are full
6 RW port0_que_full
7 RW port1_que_full
8 RW port2_que_full
9 RW port3_que_full
10 RW port4_que_full
11 RW port5_que_full
12 Reserved
13 RW CPU_que_full
14 RW Global_que_full
15 RW Must_drop

ADMtek Inc.

If port_sel=0, [24:16] port0 high packet count [8:0]
port0 low packet count
If port_sel=1, [24:16] port1 high packet count [8:0]
port1 low packet count
If port_sel=2, [24:16] port2 high packet count [8:0]
port2 low packet count
If port_sel=3, [24:16] port3 high packet count [8:0]
port3 low packet count
If port_sel=4, [24:16] port4 high packet count [8:0]
port4 low packet count
If port_sel=5, [24:16] port5 high packet count [8:0]
port5 low packet count
If port_sel=6, [24:16] port6 high packet count [8:0]
port6 low packet count
If port_sel=7, [24:16] port7 high packet count [8:0]
port7 low packet count
If port_sel=9, [8:0] flow control status
If port_sel=10, [24:16] testing [8:0] ever flow control
port
If port_sel=11, [24:16] no_pkt status [7:0]
no_pkt_status
If port_sel=12, [24:16] receive bandwidth control port ,
[8:0] transmit bandwidth control port
Description
DMA send one high priority packet to switch
DMA send one normal priority packet to switch
DMA receive one high priority packet to CPU
DMA receive one normal priority packet to CPU
meet the port0 port-th & global empty-th
meet the port1 port-th & global empty-th
meet the port2 port-th & global empty-th
meet the port3 port-th & global empty-th
meet the port4 port-th & global empty-th
meet the port5 port-th & global empty-th
Not Applicable
CPU port – meet the CPU port pre-th & global empty-th
global empty-th
all the buffer almost full
Register Description
Initial value
4-20