Mpmc Static Wait Turn [0,1,2,3] Register; Conceptual Mpmc Additional Peripheral Id Register; Mpmc Periphid4 Register, Offset Fd0H - ADMtek ADM5120 Datasheet

ADM5120
Bit # Type Name
31:5 Reserved
Note:
The wait state time for write accesses after the first read is WAITWR x tHCLK.

4.7.27 MPMC Static Wait Turn [0,1,2,3] register

Note: offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2
respectively
Bit # Type Name
3:0 R/W WAITTURN
31:4 Reserved
Note:
Bus turnaround time is (WAITTURN+1) x tHCLK.

4.7.28 Conceptual MPMC Additional Peripheral ID register

Bit # Type Name
7:0 R Configuration1
31:8 W Reserved
Note:
The configuration options are peripheral-specific. For MPMC, the four, eight-bit
peripheral identification registers are described in the following sections:

4.7.29 MPMC PeriphID4 register, offset FD0h

Bit # Type Name
0 R Configuration
2:1 R Configuration
31:3 Reserved
Note:
The MPMCPeriphID4 register is hard-coded and the fields within the register determine
the reset value.
ADMtek Inc.
Descriptions
00000 to 11110 = (n+2) HCLK cycle write access time
11111 = 33 HCLK cycle write access time (reset value
on nPOR).
Read undefined, must be written as zeros.
Descriptions
Bus turnaround cycles:
0000 to 1110 = (n+1) HCLK turnaround cycles
1111 = 16 HCLK turnaround cycles (reset value on
nPOR).
Read undefined, must be written as zeros.
Descriptions
Additional peripheral configuration information.
Read undefined, must be written as zeros.
Descriptions
Static memory interface:
0=no
1=yes (value for PL172).
Number of read/write buffers:
00=4 buffers (value for PL172)
01=8 buffers
10=12 buffers
11=16 buffers..
Read undefined, must be written as zeros.
Register Description
Initial Value
Initial Value
1111
Initial Value
0
0
Initial Value
1
00
4-49