Selectmap Clock Selection; Platform Flash Image Generation And Programming - Xilinx Virtex-4 ML455 User Manual

SelectMAP Clock Selection

SelectMAP Clock Selection
There are two clock modes for Slave SelectMAP and one clock mode for Master SelectMAP.
These modes are selected using jumpers with Header P2. The default jumper setting upon
shipment is Master SelectMAP.
Table 4-7
Mode Switch SW5.
Table 4-7: SelectMAP Clock Modes
Figure 4-8

Platform Flash Image Generation and Programming

This section provides general guidelines on how to create a PROM image file with four
different revisions (bitstreams) using the Configuration File Wizard in the iMPACT FPGA
programming tool. Online documentation from the Configuration File Wizard and
iMPACT is available through the Help -> Help Topics menu selection in iMPACT. Chapter
16 of the Xilinx Development System Reference Guide provides details on how to create a
PROM image file using PROMGen.
www.BDTIC.com/XILINX
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
shows the Virtex-4 configuration modes along with the correct settings for the
Mode
Master SelectMAP FPGA CCLK drives Flash CLKIN
(default)
Slave SelectMAP 33 MHz oscillator drives FPGA CCLK and
Flash CLKIN
Slave SelectMAP 33 MHz oscillator drives Flash CLKIN.
Flash CLKOUT drives FPGA CCLK
shows the clock structure for SelectMAP mode along with Header (P2).
U1 Flash
CLKIN
CLKOUT
U4 33 MHz Oscillator
Master SelectMAP
Slave SelectMAP
Slave SelectMAP
Figure 4-8: SelectMAP Clock Circuitry
www.xilinx.com
Function
P2 Header
1 2
3 4
6
5
R
Header P2 Jumper
Settings
1-2
1-2
3-4
1-3
5-6
U10 FPGA
CCLK
U6 CPLD
UG084_c4_08_020105
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