Xilinx Virtex-4 ML455 User Manual page 37

JTAG Port
Table 4-2: P5 JTAG Header Signal Descriptions and Pin Assignments
www.BDTIC.com/XILINX
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
Figure 4-4: Photo of ML455 Board and PC IV Pod Flat Cable Connection to P5
Signal
Description
Name
JTAG_TMS JTAG TMS to
FPGA/CPLD/
FLASH
JTAG_TCK JTAG TCK to
FPGA/CPLD/
FLASH
JTAG_TDO JTAG TDO
from FLASH
JTAG_TDI JTAG TDI to
FPGA TDI
www.xilinx.com
P5
JTAG
Connector
3.3V
1 2
3 4
5 6
7 8
9 10
11 12
13 14
2 mm
UG084_c4_03_050705
Figure 4-3: JTAG Cable Hook-up
P5 Pin FPGA Pin
Number Number
4 Y11
6 W12
8 N/A
10 Y12
TMS
TCK
TDO
TDI
CPLD Pin Flash Pin
Number Number
10
11
N/A
N/A
R
E2
H3
E6
N/A
37