Xilinx Virtex-4 ML455 User Manual page 53

In
In
www.BDTIC.com/XILINX
Virtex-4 ML455 PCI/PCI-X Development Kit
UG084 (v1.0) May 17, 2005
Figure A-4, the waveform shows destination pin U10.C13.
4500.0
4000.0
3500.0
3000.0
2500.0
2000.0
1500.0
1000.0
500.0
0.000
500.0
-
0.000 5.000 10.000
Figure A-4: Top Jumper is a Transmission Line (Hard Routed through the Net)
Figure A-5, the waveform shows destination pin U10.D2.
4500.0
4000.0
3500.0
3000.0
2500.0
2000.0
1500.0
1000.0
500.0
0.000
500.0
-
0.000 5.000 10.000
Figure A-5: Bottom Jumper is a Transmission Line (Hard Routed through the Net)
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15.000 20.000 25.000 30.000
Time (ns)
15.000 20.000 25.000 30.000
Time (ns)
35.000 40.000 45.000 50.000
UG084_apx_04_051105
35.000 40.000 45.000 50.000
UG084_apx_05_051105
R
Probe 1:U(F4)
Probe 5:U(F5)
Probe 1:U(F4)
Probe 5:U(F5)
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