Xilinx Virtex-4 ML455 User Manual page 25

64-bit PCI Edge Connector
Table 3-11: P1 PCI Edge Connector Pinout (Continued)
www.BDTIC.com/XILINX
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
P1 A Side
A9 unused
A10 VCC3V3
A11 unused
3.3V KEY
3.3V KEY
A14 2N375
A15 EDGE_RST_B
A16 VCC3V3
A17 EDGE_GNT_B
A18 GND
A19 EDGE_PME_B
A20 EDGE_AD30
A21 VCC3V3
A22 EDGE_AD28
A23 EDGE_AD26
A24 GND
A25 EDGE_AD24
A26 EDGE_IDSEL
A27 VCC3V3
A28 EDGE_AD22
A29 EDGE_AD20
A30 GND
A31 EDGE_AD18
A32 EDGE_AD16
A33 VCC3V3
A34 EDGE_FRAME_B
A35 GND
A36 EDGE_TRDY_B
A37 GND
A38 EDGE_STOP_B
A39 VCC3V3
A40 unused
www.xilinx.com
Signal P1 B Side
B9
B10
B11
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
R
Signal
GND
unused
unused
3.3V KEY
3.3V KEY
unused
GND
CLK_FROM_EDGE
GND
EDGE_REQ_B
VCC3V3
EDGE_AD31
EDGE_AD29
GND
EDGE_AD27
EDGE_AD25
VCC3V3
EDGE_CBE3
EDGE_AD23
GND
EDGE_AD21
EDGE_AD19
VCC3V3
EDGE_AD17
EDGE_CBE2
GND
EDGE_IRDY_B
VCC3V3
EDGE_DEVSEL_B
EDGE_PCIXCAP
unused
EDGE_PERR_B
25