Xilinx Virtex-4 ML455 User Manual page 39

SelectMAP Interface
Table 4-3: Pin Listing for FPGA Configuration Pins
Pin
Net Name
Number
G14 FPGA_CCLK
H12 FPGA_RDWR_B
G11 FPGA_CS_B
W15 MODE0
Y15 MODE1
W15 MODE2
H15 PROG_B
G15 INIT_B
H14 FPGA_DONE
Y14 FPGA_BUSY_B
AD13 FLASH_D0
AC13 FLASH_D1
AC15 FLASH_D2
AC16 FLASH_D3
AA11 FLASH_D4
AA12 FLASH_D5
AD14 FLASH_D6
AC14 FLASH_D7
(1, 2)
F13 FORCE
(1, 2)
F12 WIDE
(1, 2)
F11 PCIW_EN
(1, 2)
F16 RTR
D14 CPLD_SPARE1
D13 CPLD_SPARE2
D15 CPLD_SPARE3
E14 CPLD_SPARE4
C11 CPLD_SPARE5
D11 CPLD_SPARE6
D16 CPLD_SPARE7
C16 CPLD_SPARE8
E13 CPLD_SPARE9
D12 CPLD_SPARE10
Notes:
1. The Net Names and Directions for pins F13, F12, F11, and F16 were chosen to support a specific PCI/PCI-X design as described
below in "CPLD Programming Examples."
2. Use LVCMOS_25 I/O standard for general-purpose I/O connected to the CPLD.
www.BDTIC.com/XILINX
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
Direction
I/O
I
I
I
I
I
I PROGRAM_B
I
O
O DOUT_BUSY
I IO_L8N_D0_LC
I IO_L8P_D1_LC
I IO_L7N_D2_LC
I IO_L7P_D3_LC
I IO_L6N_D4_LC
I IO_L6P_D5_LC
I IO_L5N_D6_LC
I IO_L5P_D7_LC
I IO_L1N_D30_LC
I IO_L2P_D29_LC
O IO_L2N_D28_LC
O IO_L3P_D27_LC
(2)
I/O IO_L4P_D25_LC
(2)
I/O IO_L4N_D24_VREF_LC
(2)
I/O IO_L5P_D23_LC
(2)
I/O IO_L5N_D22_LC
(2)
I/O IO_L6P_D21_LC
(2)
I/O IO_L6N_D20_LC
(2)
I/O IO_L7P_D19_LC
(2)
I/O IO_L7N_D18_LC
(2)
I/O IO_L8P_D17_LC
(2)
I/O IO_L8N_D16_LC
The user can use these pins as spare, bidirectional pins.
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Pin Type
CCLK Configuration Clock Input or Output
RDWR_B Active-Low Read Write
CS_B Active-Low Chip Select
M0 Mode Select 0
M1 Mode Select 1
M2 Mode Select 2
Active-Low asynchronous full-chip reset
INIT_B Active-Low Delay Configuration Pin
DONE Active-High signal indicating
configuration is complete
Active-Low Busy signal
SelectMAP data bit 0 connected to Flash
SelectMAP data bit 1 connected to Flash
SelectMAP data bit 2 connected to Flash
SelectMAP data bit 3 connected to Flash
SelectMAP data bit 4 connected to Flash
SelectMAP data bit 5 connected to Flash
SelectMAP data bit 6 connected to Flash
SelectMAP data bit 7 connected to Flash
Input connected from Pin 31 of CPLD
Input connected from Pin 29 of CPLD
Output connected to Pin 33 of CPLD
Output connected to Pin 32 of CPLD
Spare I/O connected to CPLD pin 14
Spare I/O connected to CPLD pin 16
Spare I/O connected to CPLD pin 18
Spare I/O connected to CPLD pin 19
Spare I/O connected to CPLD pin 20
Spare I/O connected to CPLD pin 21
Spare I/O connected to CPLD pin 22
Spare I/O connected to CPLD pin 36
Spare I/O connected to CPLD pin 37
Spare I/O connected to CPLD pin 38
Description
R
39