Xilinx Virtex-4 ML455 User Manual page 52

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52
Figure A-2, the waveform shows destination pin U10.C13.
4500.0
4000.0
3500.0
3000.0
2500.0
2000.0
1500.0
1000.0
500.0
0.000
500.0
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0.000 5.000 10.000 15.000
Figure A-2: Top Jumper in Place (R2 only)
Figure A-3, the waveform shows either destination pin U10.C13 or U10.D2.
4500.0
4000.0
3500.0
3000.0
2500.0
2000.0
1500.0
1000.0
500.0
0.000
500.0
-
0.000 5.000 10.000 15.000
Figure A-3: Both Jumpers in Place (R2 and R242)
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Appendix A: PCI Bus Clock Simulations
20.000 25.000 30.000 35.000
Time (ns)
20.000 25.000 30.000 35.000
Time (ns)
Virtex-4 ML455 PCI/PCI-X Development Kit
Probe 1:U(F4)
Probe 5:U(F5)
40.000 45.000 50.000
UG084_apx_02_051105
Probe 1:U(F4)
Probe 5:U(F5)
40.000 45.000 50.000
UG084_apx_03_051005
UG084 (v1.0) May 17, 2005