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R
Table 3-6
Table 3-6: RS232 Interface Signal Names and Pin Assignments
Table 3-7
Table 3-7: Serial Interface Signal Names and Pin Assignments
Signal Name
Description
T1 (In)
Logic Level TX
R1 (Out)
Logic Level RX
R2 (Out)
Logic Level CTS
T2 (In)
Logic Level RTS
Notes:
1. MAX3316 (U5) V
= 2.5V.
CC
Figure 3-3
The RS232 DB9-F to DB9-F cable is not included in the kit. A NULL modem DB9-F to
DB9-F serial cable is required for ML455 to PC serial communications.
www.BDTIC.com/XILINX
18
describes the RS232 interface pin assignments.
Signal
Description
Name
RX (In)
Receive Data RD
TX (Out)
Transmit Data TD
RTS (Out)
Request to Send RTS
CTS (In)
Clear to Send CTS
GND
Signal Ground SG
describes the serial interface pin assignments.
MAX3316
Pin Number
(U5)
14
15
12
13
is a high-level block diagram of the RS232 interface.
U10
TX
AC12
RX
AA14
Virtex-4
FPGA
RTS
AB14
CTS
AC11
Figure 3-3: RS232 Interface Block Diagram
www.xilinx.com
DB9M (P4)
MAX3316 (U5)
Pin Number
2
3
7
8
5, 9
Signal Level
0.1 × V
to 0.9 × V
CC
CC
0.3 × V
to 0.7 × V
CC
CC
0.3 × V
to 0.7 × V
CC
CC
0.1 × V
to 0.9 × V
CC
CC
U5
T1IN
T1OUT
(14)
(17)
R1OUT
R1IN
(15)
(18)
MAX3316
T2IN
T2OUT
(13)
R2OUT
R2IN
(12)
Chapter 3: Hardware Description
Signal Level
Pin Number
Up to ±25V
16
±4V
17
±4V
8
Up to ±25V
9
18
N/A
Direction at
Pin Number
MAX3316
XC4VLX25-
(U5)
FF668 (U10)
Output
Input
Input
Output
P4
TX
3
RX
2
DB9-M
RTS
7
(8)
CTS
8
(9)
UG084_c3_02_032005
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
FPGA
AC12
AA14
AB14
AC11
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