Table of Contents
Advertisement
R
Configuration
The Virtex-4 ML455 board includes several options to configure the XC4VLX25 Virtex-4
FPGA, XC2C32 CoolRunner-II CPLD, and the XCF32PF Platform Flash. The basic
configuration modes for the Virtex-4 family are:
•
•
•
The CPLD and Platform Flash may only be configured via JTAG. The Platform Flash
contains up to four unique bitstreams for programming the FPGA. The unique
combination of the FPGA connected to the Platform Flash through the CPLD allows for
static and dynamic bitstream selection of the FPGA via Slave and Master SelectMAP
modes.
This chapter provides a description of the FPGA configuration circuitry and methods used
on the ML455 Development Board.
Configuration Modes
Table 4-1
Configuration Mode switch (SW5).
Table 4-1: Configuration Modes
Notes:
1. 0 = switch position is Closed. 1 = switch position is Open.
www.BDTIC.com/XILINX
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
JTAG mode via Parallel Cable IV or equivalent
Master SelectMap mode via CPLD/Platform Flash
Slave SelectMap mode via CPLD/Platform Flash
shows the Virtex-4 configuration modes along with the correct settings for the
Mode
Master SelectMAP
Slave SelectMAP
JTAG
www.xilinx.com
Figure 4-1
shows the Configuration Mode switch.
JTAG P5
1
(M0)
N/A
1
N/A
0
Yes
1
Chapter 4
(1)
Mode SW5
2
3
(M1)
(M2)
1
0
1
1
0
1
35
Advertisement
Table of Contents
