Xilinx Virtex-4 ML455 User Manual page 41

SelectMAP Interface
Table 4-4: Pin Listing for CPLD (Continued)
Pin
Net Name
Number
21 CPLD_SPARE6
22 CPLD_SPARE7
36 CPLD_SPARE8
37 CPLD_SPARE9
4 GND
17 GND
25 GND
15 VCC1V8
7 VCC2V5
26 VCC2V5
35 VCC2V5
Notes:
1. The Net Names and Directions for pins 29 through 33 were chosen to support a specific PCI/PCI-X design as described in
Programming Examples."
2. All CPLD I/O are 2.5V LVCMOS.
Table 4-5: Pin Listing for Flash
Pin
Net Name
Number
C1 BUSY_TO_FLASH_B
G1 CPLD_TDO
B4 FLASH_CE_B
D1 FLASH_CF_B
B3 FLASH_CLKIN
C2 FLASH_CLKOUT
H6 FLASH_D0
H5 FLASH_D1
E5 FLASH_D2
D5 FLASH_D3
C5 FLASH_D4
B5 FLASH_D5
A5 FLASH_D6
A6 FLASH_D7
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Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
Direction
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
The user can use these pins as spare, bidirectional pins.
Direction Pin Type
I
I
I
I
I
O CLKOUT
O
O
O
O
O
O
O
O
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Pin Type
IO12 Spare I/O connected to FPGA pin D11
IO13 Spare I/O connected to FPGA pin D16
IO18 Spare I/O connected to FPGA pin C16
IO19 Spare I/O connected to FPGA pin E13
GND1 Ground
GND2 Ground
GND3 Ground
VCC 1.8V Power
VCCIO1 2.5V I/O Power
VCCIO2 2.5V I/O Power
VAUX 2.5V Auxiliary Power
BUSY Active-Low Busy signal connected from CPLD
Pin 41
TDI JTAG TDI connected from CPLD JTAG TDO
CE Active-Low Chip Enable connected from CPLD
Pin 42
CF Active-Low Configuration Pulse input connected
to CPLD Pin 43
CLK Clock Input connected from Pin 1 of Header P2
Clock Output connected to Pin 5 of Header P2
D0 SelectMAP data bit 0 connected to FPGA
D1 SelectMAP data bit 1 connected to FPGA
D2 SelectMAP data bit 2 connected to FPGA
D3 SelectMAP data bit 3 connected to FPGA
D4 SelectMAP data bit 4 connected to FPGA
D5 SelectMAP data bit 5 connected to FPGA
D6 SelectMAP data bit 6 connected to FPGA
D7 SelectMAP data bit 7 connected to FPGA
Description
"CPLD
Description
R
41