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R
ML455 Board Implementation
IDSEL
The three-pin P13 IDSEL header for PCI socket J1 is wired as follows:
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M66EN - 66MHz Enable
P1.B49 is wired to two-pin header pin P9.1. With the P9 jumper shunt removed, M66EN
has a 0.01 µF capacitor to GND. Placing the jumper shunt across pins 1 and 2 of P9 shorts
M66EN to GND.
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PME# - Power Management Event
P1.A19 is wired to a two-pin header pin P7.1. PME# is pulled up on the system board. P7.2
is wired to U10 LX25 Bank 6 pin A7, allowing the FPGA to drive or sense the PME# signal
when a jumper shunt is placed across pins 1 and 2 of P7. The PCI/PCI-X LogiCore User
Guide can be consulted for more information on proper use of PME#.
PCIXCAP - PCI-X Capability
P1.B38 is wired to 3-pin header P8 (center pin).
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www.BDTIC.com/XILINX
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P13.1 - The FPGA_SPARE signal is wired to the spare FPGA I/O pin U10.R23.
P13.2 - SKT_IDSEL is wired to J1.A26 (the standard PCI socket IDSEL pin).
P13.3 - A 2 KΩ series resistor is wired to SKT_AD17, pin J1.B32.
M66EN = GND indicates 0 to 33 MHz operation.
M66EN = open indicates 33 MHz to 66 MHz operation. (M66EN is pulled up on the
system board.)
P8.1 is wired to GND through a 10KΩ pulldown resistor.
P8.2 is wired to P1.B38 and a 0.01µF capacitor to GND.
P8.3 is wired to GND.
A jumper shunt across P8 pins 1 and 2 indicates that the card is PCI-X 66 capable.
No jumper shunt across P8 indicates that the card is PCI-X 133 capable.
A jumper shunt across P8 pins 2 and 3 indicates that the card is not PCI-X capable (i.e.,
is PCI, not PCI-X).
www.xilinx.com
Chapter 3: Hardware Description
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
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