Xilinx Virtex-4 ML455 User Manual page 51

R
PCI Bus Clock Simulations
This appendix shows six simulations of the PCI clock waveforms on the Virtex-4 ML455
board. In the simulations, the split termination on the ML455 board is 100/100 ohms. The
waveforms are measured at the U10 pin on the Virtex-4 FPGA on the ML455 board. The
operation is at 133 MHz. The mother board is the Xilinx ML310, which has a 13-inch clock
trace with series and parallel resistors. For this simulation, the series R was set to 0 ohms,
and the parallel termination to GND was set to open.
Note:
the simulation source clock to account for the mother board's clock net characteristics.
The differences between the six simulations are based on the top and bottom jumpers:
•
•
•
•
•
•
In
mother board, and the Green waveform shows U10.D2 on the ML455 board.
www.BDTIC.com/XILINX
Virtex-4 ML455 PCI/PCI-X Development Kit
UG084 (v1.0) May 17, 2005
Designers should consult their mother board manuals and set the simulation parameters for
Figure A-1, Bottom Jumper in Place (R242 only)
Figure A-2, Top Jumper in Place (R2 only)
Figure A-3, Both Jumpers in Place (R2 and R242)
Figure A-4, Top Jumper is a Transmission Line (Hard Routed through the Net)
Figure A-5, Bottom Jumper is a Transmission Line (Hard Routed through the Net)
Figure A-6, Top and Bottom Jumpers are Transmission Lines (Hard Routed through
Nets)
Figure A-1, the Magenta waveform (with the highest peaks) is the clock source on the
4500.0
4000.0
3500.0
3000.0
2500.0
2000.0
1500.0
1000.0
500.0
0.000
500.0
-
0.000 5.000 10.000
Figure A-1: Bottom Jumper in Place (R242 only)
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15.000 20.000 25.000 30.000
Time (ns)
Appendix A
Probe 1:U(F4)
Probe 3:U37.R2
Probe 5:U(F5)
35.000 40.000 45.000 50.000
UG084_apx_01_051005
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