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R
Table 4-5: Pin Listing for Flash (Continued)
Pin
Net Name
Number
H4
FLASH_EN_EXT_SEL_B
A3
FLASH_OE_RESET_B
G3
FLASH_REV_SEL0
G4
FLASH_REV_SEL1
H3
JTAG_TCK
E6
JTAG_TDO
E2
JTAG_TMS
A1
GND
A2
GND
B6
GND
F1
GND
F5
GND
F6
GND
H1
GND
B1
VCC1V8
E1
VCC1V8
G6
VCC1V8
H2
VCC1V8
D6
VCC2V5
B2
VCC2V5
C6
VCC2V5
G5
VCC2V5
A4
Unused
C3
Unused
C4
Unused
D2
Unused
D3
Unused
D4
Unused
E3
Unused
E4
Unused
F2
Unused
F3
Unused
F4
Unused
G2
Unused
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42
Direction
Pin Type
I
EN_EXT_SEL Enable External Selection input – tied Low
I/O
OE/RESET
I
REV_SEL0
I
REV_SEL1
I
TCK
O
TDO
I
TMS
I
GND1
I
GND2
I
GND3
I
GND4
I
GND5
I
GND6
I
GND7
I
VCCINT1
I
VCCINT2
I
VCCINT3
I
VCCJ
I
VCCO3
I
VCCO1
I
VCCO2
I
VCCO4
I
DNC1
I
DNC2
I
DNC3
O
CEO
I
DNC4
I
DNC5
I
DNC6
I
DNC7
I
DNC8
I
DNC9
I
DNC10
I
DNC11
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Chapter 4: Configuration
Description
Output Enable / Active-Low Reset
Revision Select 0 input connected to CPLD Pin 39
Revision Select 1 input connected to CPLD Pin 40
JTAG TCK
JTAG TDO connected to Header P5
JTAG TMS
Ground
Ground
Ground
Ground
Ground
Ground
Ground
1.8V Power
1.8V Power
1.8V Power
1.8V Power
2.5V I/O Power
2.5V I/O Power
2.5V I/O Power
2.5V I/O Power
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
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