Xilinx Virtex-4 ML455 User Manual page 40

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Table 4-4: Pin Listing for CPLD
Pin
Net Name
Number
1 CPLD_CLK_33MHZ
41 BUSY_TO_FLASH_B
30 EDGE_RST_I_B
42 FLASH_CE_B
43 FLASH_CF_B
2 FLASH_IMAGE0_SELECT
3 FLASH_IMAGE1_SELECT
44 FLASH_OE_RESET_B
39 FLASH_REV_SEL0
40 FLASH_REV_SEL1
(1)
31 FORCE
6 FPGA_BUSY_B
23 FPGA_CS_B
5 FPGA_DONE
34 FPGA_RDWR_B
27 INIT_B
11 JTAG_TCK
10 JTAG_TMS
9 FPGA_TDO
24 CPLD_TDO
13 MAN_AUTO_B
12 PB_SW_B
(1)
33 PCIW_EN
28 PROG_B
8 PROG_SW_B
(1)
32 RTR
(1)
29 WIDE
14 CPLD_SPARE1
38 CPLD_SPARE10
16 CPLD_SPARE2
18 CPLD_SPARE3
19 CPLD_SPARE4
20 CPLD_SPARE5
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40
Direction
I
O
(1)
I
O
O
I
I
O
O
O
O
I
I
I
O
O
I
I
I
O
I
I
I
O
I
I
O
I/O
I/O
I/O
I
I/O
I/O
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Pin Type
IO/GC1 33 MHz Global Clock Input
IO23 Output connected to BUSY pin of Flash
IO/GS-R Input connected from Pin A15 of Edge PCI
IO24 Output connected to /CE pin of Flash
IO/GC2 Output connected to /CF pin of Flash
IO1 Revision Select Pin 0 from Header P3
IO2 Revision Select Pin 1 from Header P3
IO/GC3 Output connected to OE_/RESET pin of Flash
IO21 Output connected to REV_SEL0 pin of Flash
IO22 Output connected to REV_SEL1 pin of Flash
IO/GOE1 Output connected to Pin F13 of FPGA
IO4 DOUT Busy pin from FPGA
IO14 Chip Select from FPGA
IO3 DONE pin from FPGA
IO/GOE4 Output connected to RDWR_B pin of FPGA
IO15 Output connected to INIT_B pin of FPGA
TCK JTAG TCK
TMS JTAG TMS
TDI JTAG TDI from FPGA
TDO JTAG TDO to Flash
IO7 Manual/Auto Select pin from Header P3
IO6 Input from Push Button SW7
IO/GOE3 Input connected from Pin F11 of FPGA
IO16 Output connected to PROG_B pin of FPGA
IO5 Input from Push Button SW6
IO/GOE2 Input connected from Pin F16 of FPGA
IO17 Output connected to Pin F12 of FPGA
IO8 Spare I/O connected to FPGA pin D14
IO20 Spare I/O connected to FPGA pin D12
IO9 Spare I/O connected to FPGA pin D13
I Spare Input connected to FPGA pin D15
IO10 Spare I/O connected to FPGA pin E14
IO11 Spare I/O connected to FPGA pin C11
Chapter 4: Configuration
Description
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005