Xilinx Virtex-4 ML455 User Manual page 26

R
Table 3-11: P1 PCI Edge Connector Pinout (Continued)
64-Bit Connector
www.BDTIC.com/XILINX
26
P1 A Side
A41 unused
A42 GND
A43 EDGE_PAR
A44 EDGE_AD15
A45 VCC3V3
A46 EDGE_AD13
A47 EDGE_AD11
A48 GND
A49 EDGE_AD9
A50 GND
A51 GND
A52 EDGE_CBE0
A53 VCC3V3
A54 EDGE_AD6
A55 EDGE_AD4
A56 GND
A57 EDGE_AD2
A58 EDGE_AD0
A59 VCC3V3
A60 EDGE_REQ64_B
A61 VCC5
A62 VCC5
A63 GND
A64 EDGE_CBE7
A65 EDGE_CBE5
A66 VCC3V3
A67 EDGE_PAR64
A68 EDGE_AD62
A69 GND
A70 EDGE_AD60
A71 EDGE_AD58
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Chapter 3: Hardware Description
Signal P1 B Side
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
Signal
VCC3V3
EDGE_SERR_B
VCC3V3
EDGE_CBE1
EDGE_AD14
GND
EDGE_AD12
EDGE_AD10
EDGE_M66EN
GND
GND
EDGE_AD8
EDGE_AD7
VCC3V3
EDGE_AD5
EDGE_AD3
GND
EDGE_AD1
VCC3V3
EDGE_ACK64_B
VCC5
VCC5
unused
GND
EDGE_CBE6
EDGE_CBE4
GND
EDGE_AD63
EDGE_AD61
VCC3V3
EDGE_AD59
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005