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General-Purpose I/O and LCD Header
General-Purpose I/O and LCD Header
P11 is a 2 x 9 male pin header providing two functions:
•
•
Figure 3-4
Table 3-8
Table 3-8: General-Purpose Header P11
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Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
General-purpose I/O header for logic analysis and so forth. Fifteen of the 16 test pins
(TEST[16:1]) are wired directly to the U10 LX25 Bank 9 I/O pins. Signal TEST1 is
wired to P11.3 using a 0 Ω resistor R243. This resistor is typically removed when P11 is
used to support LCD operation (described below). There are no pull-up or pull-down
resistors on these test signals. When this header is used in this (general-purpose)
mode, P11 pins 1 and 2 normally are unused. R243 (0 Ω) is installed, and R244 and
R245 are removed.
Optional LCD support mode. The signals wired to P11 can optionally be assigned
LCD interface functions. The 2 x 9 header is pinned out to match most standard LCD
modules. P11 pins 1 and 2 can each be wired to either GND or V
from an array of available voltages via the placement of a 0 Ω resistor (one only) at
locations R252 (5V) or R253 (3.3V) or R254 (SKT_VCCO). SKT_VCCO can be either
3.0V or 2.5V, selected at the 3-pin header P18. For the LCD mode, R243 is removed,
and R244 and R245 are installed to provide the LCD contrast voltage required by most
LCD modules. The values of R244 and R245 are calculated for a specific LCD display,
since LCD displays have different LCD_DRIVE contrast voltage settings.
shows the P11 header with one possible, optional LCD signal assignment.
R243
TEST1
TEST3
0
TEST5
TEST7
TEST9
TEST11
TEST13
TEST15
lists the pinout of the P11 header for both General-Purpose and LCD modes.
Signal Name
GP Mode
GND
VCC or GND
VCC
VCC or GND
test1
LCD_DRIVE
test2
LCD_DATA7
test3
LCD_DATA6
test4
LCD_DATA5
test5
LCD_DATA4
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R250
R248
DNA
DNA
P11
R251
R249
1
2
3
4
TEST2
5
6
TEST4
7
8
TEST6
9
10
TEST8
11
12
TEST10
13
14
TEST12
15
16
TEST14
17
18
TEST16
Figure 3-4: P11 Header
P11 Pin #
LCD Mode
. V
is selected
CC
CC
5V
3.3V
SKT_VCCO
C306
0.1 µF
UG084_c3_05_042605
FPGA Pin #
1
no connect
2
no connect
3
N21
4
N20
5
P24
6
P23
7
P20
R
19
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