User Push-Button Switches; Push-Button Program Switch (Sw6); Push-Button Reset Switch (Sw7); Rs232 Port - Xilinx Virtex-4 ML455 User Manual

User Push-Button Switches

User Push-Button Switches
The ML455 board provides four user push-button switches. The switch outputs are pulled
up to 2.5V using 4.7 KΩ resistors on the board. The push buttons generate a switch closure
to GND when pressed. Switch contact debounce logic must be implemented inside the
FPGA.
Table 3-5: User Push-Button Switch Assignments

Push-Button Program Switch (SW6)

The ML455 board provides a push-button program switch for initiating reconfiguration of
the Virtex-4 FPGA. A CPLD image is provided with the ML455 board to enable pressing
and releasing the program push-button switch (SW6) to initiate a full FPGA device
configuration cycle while the board is powered on. The CPLD design files and bit image
are on the reference CD included in the kit. Pressing this switch causes the FPGA to clear
its internal configuration memory and then load the currently selected image (via the P3
image select jumper block) from the Platform Flash (U1).

Push-Button Reset Switch (SW7)

The ML455 board provides a push-button switch SW7 for a user-assigned function. This
switch, labelled RESET, is wired to the CPLD U6 pin 12 (general-purpose I/O pin). The
switch output is connected by a 4.7 KΩ pull-up resistor to 2.5V. This push button generates
a switch closure to GND when pressed. Switch contact debounce logic must be
implemented inside the CPLD. There are multiple connections between the CPLD U6 and
the FPGA U10 to transmit SW7 activity. Refer to schematic sheet 14.

RS232 Port

The ML455 board provides a DB9-M (P4) connector for the RS232 port. The board uses the
Maxim MAX3316ECUP (U5) device to drive the RD, TD, RTS, and CTS signals. The
MAX3316 RS232 interface device operates from a 2.5V supply. The interface between the
MAX3316 and the FPGA is at LVCMOS_25 standard levels. Charge pump capacitors allow
the MAX3316 connector (P4) RS232 interface signals a nominal ± 4V swing up to 460 kb/s
data rate. The user must provide a UART core internal to the FPGA to enable serial
communication.
www.BDTIC.com/XILINX
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
Table 3-5 lists the FPGA pin assignments.
Push-Button Switch Signal
USER_SW0
USER_SW1
USER_SW2
USER_SW3
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Description
USER1 SW1
USER2 SW2
USER3 SW3
USER4 SW4
FPGA Pin Number
(FF668 Package)
AF12
AE12
AC10
AB10
17
R