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R
Generic Dynamic Reconfiguration
It is possible to dynamically reconfigure the entire FPGA after power-up. With this
method, the CPLD loads a predetermined, default bitstream from the Platform Flash upon
power-up. After initial configuration, the FPGA can signal to the CPLD that it wants to be
reconfigured with a different bitstream, using the CPLD_SPARE[1:10] pins. The FPGA
simply specifies the bitstream revision along with a signal to indicate when to start the
configuration process. Logic within the CPLD then controls the configuration pins to the
FPGA and Platform Flash to complete the configuration cycle. This logic can be as simple
as driving the REV_SEL pins to the Flash and the PROG_B pin on the FPGA to begin
configuration. The MAN_AUTO_B input to the CPLD can be incorporated into the design
to override the dynamic reconfiguration and allow only static configuration as described
in XAPP693: A CPLD-Based Configuration and Revision Manager from Xilinx Platform Flash
PROMs and FPGAs. This application note provides details on using a CPLD and Platform
Flash to dynamically reconfigure an FPGA.
The PCI-X LogiCORE Getting Started Guide can be consulted for information on using the
FORCE, WIDE, PCIW_EN, and RTR signals to support dynamic reconfiguration.
U1
Platform Flash
XCF32PF
To P2
CLKOUT
CLKIN
From P2
Notes:
1. FORCE, WIDE, PCIW_EN, and RTR are FPGA general-purpose I/Os.
Figure 4-7: CPLD Configuration for Dynamic Reconfiguration
www.BDTIC.com/XILINX
44
D[0:7]
CE
BUSY
42
41
CF
43
OE/RESET
44
REV_SEL0
39
REV_SEL1
40
12 8 2
P3
1
2
3
4
5
6
www.xilinx.com
Figure 4-7
illustrates this method.
8
U6
31
CPLD
29
XC2C32
33
32
5
6
34
23
28
27
State Machine
and Logic
10
2
1
3 13
33 MHz
CPLD
CLK
Chapter 4: Configuration
U10
FPGA
D[7:0]
XC4VLX25
(1)
FORCE
(1)
WIDE
(1)
PCIW_EN
(1)
RTR
DONE
DOUT_BUSY
RDWR_B
CS_B
PROG_B
INIT_B
CPLD_SPARE[1:10]
CCLK
M0 M1 M2
From/To P2
SW5
DIP SW
UG084_c4_07_051105
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
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