Power And System Management - ADLINK Technology intel COM Express Express-TL User Manual

Express-TL User's Guide

4.3.15 Power and System Management

Name Pin # Description
PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge.
SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May be
falling edge sensitive. For situations when SYS_RESET# is not able to reestablish
control of the system, PWR_OK or a power cycle may be used.
CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module chipset
and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V
power input that falls below the minimum specification, a watchdog timeout, or
may be initiated by the module software.
PWR_OK B24 Power OK from main power supply. A high value indicates that the power is good.
This signal can be used to hold off Module startup to allow carrier-based FPGAs or
other configurable devices time to be programmed.
SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices.
SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted copy
of SUS_S3# on the carrier board (also known as "PS_ON") may be used to enable
the non-standby power on a typical ATX power supply.
SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output.
SUS_S5# A24 Indicates system is in Soft Off state.
WAKE0# B66 PCI Express wake up signal.
WAKE1# B67 General purpose wake-up signal. May be used to implement wake-up on PS/2
keyboard or mouse activity.
BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to signal that
the system battery is low or may be used to signal some other external power-
management event.
LID# A103 LID button. Low active signal used by the ACPI operating system for a LID switch.
SLEEP# B103 Sleep button. Low active signal used by the ACPI operating system to bring the
system to sleep state or to wake it up again.
Trigger for Rapid Shutdown. Must be driven to 5V though a <=50-ohm source
RAPID_ C67
impedance for ≥ 20 μs.
SHUTDOWN
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I/O PU / PD Comment
I 3.3VSB PU 10K 3.3VSB
I 3.3VSB PU 10K 3.3VSB
O
3.3V
I 3.3VSB PU 10K 3.3VSB Should have weak pull up.
O 3.3VSB
O 3.3VSB PD 100K
O 3.3VSB PD 100K
O 3.3VSB PD 100K
I 3.3VSB PU 10K 3.3VSB
I 3.3VSB PU 10K 3.3VSB Connect to WAKE 0#
I 3.3VSB PU 10K 3.3VSB
I OD 3.3VSB PU 47K 3.3VSB Emulated on GPIO (BIOS)
I OD 3.3VSB PU 47K 3.3VSB Emulated on GPIO (BIOS)
I CMOS Not supported
5VSB
PICMG COM.0 R3.0