Block Diagram; Figure 1 - Module Function Diagram - ADLINK Technology intel COM Express Express-TL User Manual

Express-TL User's Guide

3. Block Diagram

USB 2.0 Lane 0-7
SATA Port 0-3
Max. 2.5GbE
PCIe Lane 0-3
PCIe Lane 4-5
8xGPIO/SDIO
2xUART/CAN
Page 18
ECC, non-ECC dependent on CPU/chipset config.
DDR4 SODIMM
DDR4 SODIMM
3200 MT/s
up to 3200 MT/s
DDR4 SODIMM
DDR4 SODIMM
3200 MT/s
up to 3200 MT/s
3 ,4 socket dependent on SKU
rd th
DDI B
eDP/LVDS
(eDP 4lanes)
eDP to LVDS
eDP x4
VGA
DP to VGA
SATA 6Gb/s
LAN Controller
Intel I225
1 PCIe Gen3
TSN dependent on controller SKU
1 x4, 2 x2, 4 x1
4 PCIe Gen3
2 x1
2 PCIe Gen3
1 x4 (Lane 4-7)
HDA
BIOS BIOS
Flash Flash
SPI
TPM 2.0
SMBus
I2C
HSUART
LPC/eSPI
Figure 1 – Module function diagram
Copyright © 2022 ADLINK Technology, Inc.
Intel® Xeon®
TCP 0
11 Gen Intel® Core™/Celeron®
th
Processor
TCP 1
TCP 2
(Tiger Lake-H)
16 PCIe Gen4
DMI (x8, Gen3)
USB 3.2 Gen2 x1
USB 3.2 Gen2 x1
USB 3.2 Gen2 x1
USB 3.2 Gen2 x1
2 PCIe Gen3
Mobile Intel
Next Series Chipset
2 PCIe Gen3
RM590E/QM580E/HM570E
1 PCIe Gen4 x4
2 MIPI-CSI
eSPI
eSPI
eSPI to LPC
Fan
Connector
Embedded
Controller
LM73
(board)
DDI 1 / USB4
DDI 2 / USB4
DDI 3
PEG Port
1 x16 or 2 x8
or 1 x8 + 2 x4 PCIe 16 -31
USB 3.0 Lane 3
USB 3.0 Lane 2
USB 3.0 Lane 1
USB 3.0 Lane 0
2 x1
PCIe Lane 6-7
1 x4 (Lane 4-7)
build option
x2
BGA SSD
DB30 x86
Connector
PICMG COM.0 R3.0