Download
Share
Print this page
  1. Manuals
  2. Brands
  3. ADLINK Technology Manuals
  4. Computer Hardware
  5. I-Pi SMARC
  6. User manual

ADLINK Technology I-Pi SMARC User Manual

Hide thumbs

Advertisement

Quick Links

Download this manual
COM-HPC-cRLS User's Guide
I-Pi SMARC
Page 1
User's Guide
Revision:
Rev. 0.5
Date:
2024-07-10
Part Number:
50M-77A07-1000
Copyright © 2024 ADLINK Technology, Inc.
PICMG COM-HPC R1.1

Advertisement

loading
Need help?

Need help?

Do you have a question about the I-Pi SMARC and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for ADLINK Technology I-Pi SMARC

Summary of Contents for ADLINK Technology I-Pi SMARC

  • Page 1 COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 I-Pi SMARC User’s Guide Revision: Rev. 0.5 Date: 2024-07-10 Part Number: 50M-77A07-1000 Page 1 Copyright © 2024 ADLINK Technology, Inc.
  • Page 2 Revision History Revision Description Date Preliminary release 2024-03-26 Pin definitions updated 2024-05-14 Images updated 2024-06-14 Illustrations and labels updated 2024-07-05 Fan pin definitions added 2024-07-10...
  • Page 3 Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. Copyright © 2024 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
  • Page 4 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. • Page 4 copyright © 2024 ADLINK Technology Inc.
  • Page 5 Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. Page 5 copyright © 2024 ADLINK Technology Inc.
  • Page 6 ADLINK Technology GmbH Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. Page 6 copyright © 2024 ADLINK Technology Inc.
  • Page 7 1st LAN ..................................................................20 5.8.2 2nd LAN ..................................................................21 SDIO ......................................................................22 5.10 SPI & ESPI ....................................................................23 5.10.1 SPI0 ....................................................................23 5.10.2 ESPI ....................................................................24 5.11 General Purpose I2C ................................................................25 Page 7 copyright © 2024 ADLINK Technology Inc.
  • Page 8 5.13 UART ......................................................................27 5.14 CAN Bus ..................................................................... 28 5.15 Miscellaneous..................................................................28 5.16 Power and System Management ............................................................ 29 5.16.1 Boot Select ................................................................... 31 5.16.2 Power ..................................................................... 32 6. Mechanical ..............................................................33 Page 8 copyright © 2024 ADLINK Technology Inc.
  • Page 9 The modular approach allows scalability, accelerated time-to-market and upgradability while still maintaining low costs, low power, and small physical size. SMARC module and carrier specifications are available online at https://www.sget.org/standards/smarc.html Page 2 copyright © 2024 ADLINK Technology Inc.
  • Page 10 SGET SMARC Rev 2.1 2. Specifications 2.1 Boot Modes The standard boot mode of the I-Pi SMARC Plus is configured as an SD-card boot. Other boot options are supported by a boot-selector switch located on the carrier. 2.2 Power Supply The I-Pi SMARC Plus is powered by a 5.5 mm barrel connector, the supply voltage is 19V DC.
  • Page 11 USB3 - 3.0 Host USB 3.0 Host USB2 - 3.0 Host PCIe-B M.2 B-Key MUX USB2 RJ45 GBE0 GBE1 RJ45 USIM Micro SD SDIO SMARC 2.1 Reset MXM 3.0 Power I2S0 Audio expansion Boot-Select Page 4 copyright © 2024 ADLINK Technology Inc.
  • Page 12 GPIO1_2 / PWM ESPI RESET_N GPIO1_3 / PWM HDMI#_SEL_H M.2 USB3.0 GPIO1_4 / PWM GPIO1_5 / PWM MUX SEL_H GPIO1_6 / PWM GPIO1_7 / PWM HDMI#_SEL M.2 USB 3.0 GPIO2_8 / PWM MUX SEL Page 5 copyright © 2024 ADLINK Technology Inc.
  • Page 13 LVDS0_EDP0_DSI0_D2_CN_P DDC1_DAT LVDS1_EDP1_DSI1_CK_CN_P LVDS_BKLT0_EN LVDS0_EDP0_DSI0_D2_CN_N DDC1_CK LVDS1_EDP1_DSI1_CK_CN_N LVDS_BKLT0_EN LVDS0_EDP0_DSI0_D3_CN_P LCD0_VDD_EN_3V3 LVDS0_EDP0_DSI0_D3_CN_N eDP0_HPD_DSI0_TE_3V3 DDC0_DAT LVDS0_EDP0_DSI0_CK_CN_P DDC0_CK LVDS0_EDP0_DSI0_CK_CN_N Both connectors use the same pin-out, connector 1 on the left, connector 0 on the right. Page 6 copyright © 2024 ADLINK Technology Inc.
  • Page 14 CSI1_D1_P Output MIPI Data Lane 1 Positive CSI1_D1_N Output MIPI Data Lane 1 Negative Power Ground CSI1_D0_P Output MIPI Data Lane 0 Positive CSI1_D0_N Output MIPI Data Lane 0 Negative Power Ground Page 7 copyright © 2024 ADLINK Technology Inc.
  • Page 15 HDMI coupling 35-37 = AC | 37-39 = DC SMARC power sequence On = 2.1 | Off = 2.0 LVDS-EL Can Bus 3.3-5V Termination SPI1 1.8-3.3V HDMI SMARC 2.0/2.1 coupling Power sequence Page 8 copyright © 2024 ADLINK Technology Inc.
  • Page 16 I-Pi-SMARC User’s Guide SGET SMARC Rev 2.1 Audio codec mezzanine The I-Pi SMARC Plus is equipped with an interchangeable audio codec. Multiple codecs are available in I2S, HDA or SoundWire. The board uses a one-screw fixation that sits the codecs in a board- to-board connector.
  • Page 17 Level shifter FET and 5V PU resistor shall be placed COMS between the module and the HDMI connector. HDMI_HPD P104 HDMI Hot plug active high detection 1.8V Standby signal that serves as an interrupt CMOS request Page 10 copyright © 2024 ADLINK Technology Inc.
  • Page 18 Not supported LVDS1_CK- S109 clock lines. LCD1_VDD_EN S116 Secondary panel power enable, active high 1.8V Runtime Not supported CMOS LCD1_BKLT_EN S107 Secondary panel backlight enable, active 1.8V Runtime Not supported high CMOS Page 11 copyright © 2024 ADLINK Technology Inc.
  • Page 19 Primary panel backlight enable, active 1.8V Runtime high CMOS LCD0_BKLT_PWM S141 Primary panel brightness control through 1.8V Runtime pulse width modulation (PWM) CMOS DSI0_TE S144 Primary DSI panel tearing effect sigal 1.8V Runtime CMOS Page 12 copyright © 2024 ADLINK Technology Inc.
  • Page 20 CAM0_RST# / P110 Camera 0 reset, active low output O CMOS 1.8V Runtime GPIO2 CAM_MCK Master clock output O CMOS 1.8V Runtime This signal is used by both CSI0 and CSI1 Page 13 copyright © 2024 ADLINK Technology Inc.
  • Page 21 Camera 0 reset, active low output O CMOS 1.8V Runtime CAM1_PWR# is default, GPIO3 can be enabled GPIO3 through DVT CAM_MCK Master clock output O CMOS 1.8V Runtime This signal is used by both CSI0 and CSI1 Page 14 copyright © 2024 ADLINK Technology Inc.
  • Page 22 1.8V Runtime codec(s) CMOS Note: 1. I2S signals are routed to the Audio Expansion Board pin header. 2. Support for I2S1 signalling pins has been removed during update to SMARC 2.0 specification. Page 15 copyright © 2024 ADLINK Technology Inc.
  • Page 23 CMOS HDA_RST# / P112 High Definition Audio reset output 1.8V / 1.5V Runtime GPIO4 to codec, low active. CMOS Note: HDA signals are routed to the Audio Expansion Board pin header. Page 16 copyright © 2024 ADLINK Technology Inc.
  • Page 24 USB differential data pairs for port 3 Standby USB3- USB3_SSRX+ Receive signal differential pairs for USB SS Standby Coupling caps for RX pairs are on the USB Device USB3_SSRX- SuperSpeed on port 3 USB SS Page 17 copyright © 2024 ADLINK Technology Inc.
  • Page 25 Pulled low by Module OD driver to disable USB0 power. Pulled CMOS low by Carrier OD driver to indicate over-current situation. Note: USB0 is directly connected to the SoC, USB1/2/3/4 might come over a USB hub on the SMARC module. Page 18 copyright © 2024 ADLINK Technology Inc.
  • Page 26 PU 10k common to PCIe links A, B, C, D CMOS Note: The module provides PCIe clock generators for PCIE_A and PCIE_B, thus not external clock source on the carrier is needed. Page 19 copyright © 2024 ADLINK Technology Inc.
  • Page 27 Center-Tap reference voltage for Carrier board Ethernet Analog 0 to Runtime magnetic (if required by the Module GBE PHY) 3.3V max GBE0_SDP IEEE 1588 Trigger Signal. For hardware implementation 3.3V Runtime of PTP (precision time protocol) CMOS Page 20 copyright © 2024 ADLINK Technology Inc.
  • Page 28 `(if required by the Module GBE PHY)` GBE1_SDP IEEE 1588 Trigger Signal. For hardware implementation 3.3V Runtime of PTP (precision time protocol) CMOS Note: The number of functional LAN ports is dependent on the module used. Page 21 copyright © 2024 ADLINK Technology Inc.
  • Page 29 SDIO_PWR_EN SDIO Power Enable. This signal is used to 3.3V Runtime should be driven low in STB Mode by the enable the power being supplied to a SD/MMC card CMOS module device. Page 22 copyright © 2024 ADLINK Technology Inc.
  • Page 30 1.8V Standby See ESPI CMOS SPI1_DO SPI1 Master output / Slave input 1.8V Standby See ESPI CMOS Note: SPI0 on RPI header, SPI1 on plus header. See jumper settings for SPI voltage. Page 23 copyright © 2024 ADLINK Technology Inc.
  • Page 31 ESPI_IO_1 can also be used as SPI1_DIN (MISO) ESPI_IO_2 ESPI_IO_3 In Single I/O mode, ESPI_IO_0 is the eSPI master output / eSPI slave input (MOSI) whereas ESPI_IO_1 is the SPI master input / eSPI slave output (MISO). Page 24 copyright © 2024 ADLINK Technology Inc.
  • Page 32 I2C clock for serial camera data support link MIPI CSI table I2C_PM_DAT P122 Power management I2C bus DATA (SMBus for x86) Power and System Management I2C_PM_CK P121 Power management I2C bus CLK (SMBus for x86) Power and System Management Page 25 copyright © 2024 ADLINK Technology Inc.
  • Page 33 General purpose I/O pin 1.8V Runtime PU 470K on the CMOS Module GPIO13 S123 General purpose I/O pin 1.8V Runtime PU 470K on the CMOS Module Note: All GPIO are on RPI header. Page 26 copyright © 2024 ADLINK Technology Inc.
  • Page 34 CMOS SER3_TX P140 Asynchronous serial data output port 3 1.8V Runtime CMOS SER3_RX P141 Asynchronous serial data input port 3 1.8V Runtime CMOS Note: SER0 on RPI header, SER1,2,3 on plus header. Page 27 copyright © 2024 ADLINK Technology Inc.
  • Page 35 Driven by OD depended on particular module design. Carrier function(s). on Carrier Board should leave this pin floating for normal operation WDT_TIME_OUT# S145 Watch-Dog-Timer Output, low 1.8V Runtime Driven only during runtime active. CMOS Page 28 copyright © 2024 ADLINK Technology Inc.
  • Page 36 Active low, level CMOS Pulled up on module. sensitive. Should be debounced on the Module. RESET_OUT# P126 General purpose reset output to Carrier board. 1.8V Runtime CMOS Page 29 copyright © 2024 ADLINK Technology Inc.
  • Page 37 PU 2k2 On x86 systems these serve as SMB CLK. CMOS Pulled up on module. SMB_ALERT_1V8# SMBus Alert# (interrupt) signal I OD 1.8V Runtime PU 2k2 only used on x86 design CMOS Page 30 copyright © 2024 ADLINK Technology Inc.
  • Page 38 0 0 1 0 SPI 0 1 0 0 Remote Gbe 1 0 0 0 eMMC (SoM) 0 0 0 1 Force Recovery Note: Boot selector switch is located between the SoM and LAN ports. Page 31 copyright © 2024 ADLINK Technology Inc.
  • Page 39 – 3.0V nominal. May be Terminolgy Descriptions. sourced from a Carrier based Should we define a specific Lithium cell or Super Cap. rail? Note: The DC jack’s input voltage level is19V DC. Page 32 copyright © 2024 ADLINK Technology Inc.
  • Page 40 I-Pi-SMARC User’s Guide SGET SMARC Rev 2.1 6. Mechanical Note: Carrier fixation holes are made for M3 screws. SMARC modules are fixed by M3 screws, with lengths dependent on the heatsink used. Page 33 copyright © 2024 ADLINK Technology Inc.