Pmc Connector (Jh1 & Jh2) - Altera Nios Cyclone II Edition Reference Manual

Board Components
f
PMC Connector
(JH1 & JH2)
2–26
Nios Development Board Cyclone II Edition
Table 2–13. CompactFlash Pin Table (Continued)
FPGA Pin CON3 Pin
V23 43
Y22 44
W16 32
AE16 9
AD16 5
W15 26
56 (U3) 41
Notes to Table 2–13:
(1) Nets proto_io16, proto_io20, and proto_io21 do not connect to CON3.
(2) The FPGA I/O pin controls a power MOSFET that supplies 5V VCC to this net.
(3) proto1_RESET_n is driven by the EPM7256AE configuration controller device
(U3).
For more information on the CompactFlash connector (CON3), see
www.compactflash.org and www.molex.com.
The PCI mezzanine card (PMC) connector, formed by JH1 and JH2,
allows Nios II systems in the FPGA to interface to daughter cards using
the standard 32-bit PMC form factor. Refer to
connector is capable of 33MHz and 66 MHz, and is configured as the PMC
host.
w Before connecting a daughter card to the PMC connector, the
FPGA must first be configured with a design that includes a
PMC interface. Damage to either the FPGA or daughter card can
result if the FPGA is not configured correctly.
The factory-programmed Nios II reference design does not include a
PMC interface.
Reference Manual
Pin Function Board Net Name
INPACK_n proto1_io39
REG_n proto1_io40
CS1_n cf_cs_n
ATA_SEL_n cf_atasel_n
Power supply cf_power
enable
CD1_n cf_present_n
RESET# proto1_RESET_n
Figure 2–11. The PMC
Altera Corporation
(1)
(2)
(3)
May 2007