Altera Nios Cyclone II Edition Reference Manual page 55

Altera Corporation
May 2007
The FPGA receives clock input from buffer U2, and from the PROTO1 and
PROTO2 connectors, as shown in
Table 2–21. FPGA Clock Input Pin Table
FPGA Pin FPGA Pin Name
B25 IO
N26 CLK5
AF4 CLK13
P25 CLK6
AC13 CLK15
N2 CLK0
B13 CLK8
The FPGA can synthesize new clock signals internally using on-chip
PLLs, and drive the clocks to various components on the board, as shown
in Table 2–22.
Table 2–22. FPGA Clock Output Pin Table
FPGA Pin FPGA Pin Name
AA7 PLL1_OUTp
AA6 PLL1_OUTn
E5 PLL3_OUTp
W26 IO
F21 PLL2_OUTp
F20 PLL2_OUTn
V21 PLL4_OUTp
Note to Table 2–22:
(1) PLLs are only dedicated when using the Enhanced PLL. If you use the Fast PLL,
the PLL inputs and outputs are interchangeable. For more information on using
PLLs in the Cyclone II refer to the data sheet.
The 50 MHz oscillator (Y2) is socketed and can be changed or removed by
the user. To drive the clock circuitry using the external clock connector
(J4), remove Y2.
1
The factory-programmed configuration controller and Altera-
provided reference designs work only with the 50 MHz clock.
Reference Manual
Table 2–21.
PLL Signal Source
N/A J25 pin 6
PLL2 J13 pin 13
PLL4 J17 pin 13
PLL2 U2 pin 2
PLL4 U2 pin 3
PLL1 U2 pin 4
PLL3 U2 pin 6
Signal
PLL (1)
Destination
PLL1 U63 pin 45
PLL1 U63 pin 46
PLL3 U74 pin 89
N/A JH1 pin 13
PLL2 J13 pin 11
PLL2 J17 pin 11
PLL4 J25 pin 5
Nios Development Board Cyclone II Edition
Board Components
Board Net Name
mictor_TRCLK
proto1_CLKOUT
proto2_CLKOUT
osc_CLK0
osc_CLK1
sram_CLKIN
sdram_CLKIN
Board Net Name
sdram_CLK_p
sdram_CLK_n
sram_CLK
pmc_CLK
proto1_PLLCLK
proto2_PLLCLK
mictor_CLK
2–43