Ddr Sdram Chip (U63) - Altera Nios Cyclone II Edition Reference Manual

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DDR SDRAM
Chip (U63)
Altera Corporation
May 2007
Table 2–6. SSRAM Pin Table (Continued)
FPGA Pin
K9 88
E5 89
The following pins on U74 have fixed connections, which restricts the
usable modes of operation:
■
MODE is pulled low to enable Linear Burst
■
ZZ is pulled low to leave the chip enabled
■
GLOBALW_n is pulled high to disable the global write
■
CE2 and CE3_n are wired high and low respectively to be enabled
and to make CE1_n the master chip enable
See www.cypress.com for detailed information about the SSRAM chip.
U63 is a Micron DDR SDRAM chip. Depending on the board revision, the
part number is MT46V16M16TG or MT46V16M16P-6T. The DDR
SDRAM pins are connected to the FPGA as shown in
provides a DDR SDRAM controller that allows a Nios II processor to
access the DDR SDRAM device as a large, linearly-addressable memory.
Table 2–7. DDR SDRAM Pin Table
FPGA Pin U63 Pin
R2 2
R3 4
R4 5
P7 7
P6 8
T2 10
T3 11
R6 13
W2 54
W1 56
U6 57
U7 59
U5 60
Y1 62
Reference Manual
U74 Pin Pin Function
GW_n
CLK
Board Net Name
sdram_dq0
sdram_dq1
sdram_dq2
sdram_dq3
sdram_dq4
sdram_dq5
sdram_dq6
sdram_dq7
sdram_dq8
sdram_dq9
sdram_dq10
sdram_dq11
sdram_dq12
sdram_dq13
Nios Development Board Cyclone II Edition
Board Components
Board Net Name
ssram_gw_n
sram_clk
Table 2–7. Altera
2–9