Push-Button Switches (Sw0 - Sw3) - Altera Nios Cyclone II Edition Reference Manual

Board Components
f
Push-Button
Switches (SW0 -
SW3)
2–4
Nios Development Board Cyclone II Edition
The development board provides two separate methods for configuring
the FPGA:
1. Using the Quartus
designer configures the device directly via an Altera download
cable connected to the FPGA JTAG header (J24).
2. When power is applied to the board, a configuration controller
device (U3) attempts to configure the FPGA with hardware
configuration data stored in flash memory. For more information on
the configuration controller, refer to
Device (U3)" on page
For Cyclone II-related documentation including pin out data for the
EP2C35 device, see the Altera Cyclone II literature page at
www.altera.com/literature/lit-cyc2.jsp.
SW0 – SW3 are momentary-contact push-button switches to provide
stimulus to designs in the FPGA. Refer to
connected to an FPGA general-purpose I/O pin with a pull-up resistor as
shown in Table 2–3. Each I/O pin perceives a logic 0 when its
corresponding switch is pressed.
Figure 2–2. Push-Button Switches (SW0 – SW3)
D0 D1 D2
SW0
Table 2–3. Push Button Switches Pin Table
Button
SW0 Y11
SW1 AA10
SW2 AB10
SW3 AE6
Reference Manual
®
II software running on a host computer, a
"Configuration Controller
2–33.
Figure
D3 D4
SW1 SW2
FPGA Pin
user_pb0
user_pb1
user_pb2
user_pb3
2–2. Each switch is
D5 D6 D7
SW3
Board Net Name
Altera Corporation
May 2007