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- Page 1 Nios Development Board Reference Manual, Cyclone Edition 101 Innovation Drive Document Version: San Jose, CA 95134 Document Date: January 2004 (408) 544-7000 www.altera.com...
- Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
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Page 3: About This Manual
About this Manual This manual provides component details about the Nios development board, Cyclone edition. Table 1 shows the reference manual revision history. Table 1. Reference Manual Revision History Date Description January 2004 Pin table corrections. July 2003 Reflects new directory structure for SOPC Builder 3.0 and Nios Development Kit version 3.1. -
Page 4: How To Contact Altera
(800) 800-EPLD (3753) (408) 544-7000 (7:30 a.m. to 5:30 p.m. (7:30 a.m. to 5:30 p.m. Pacific Time) Pacific Time) http://www.altera.com/mysupport/ http://www.altera.com/mysupport/ FTP site ftp.altera.com ftp.altera.com Note: You can also contact your local Altera sales office or sales representative. Altera Corporation... -
Page 5: Typographic Conventions
Nios Development Board, Cyclone Edition Reference Manual About this Manual Typographic This manual uses the typographic conventions shown in Table Conventions Table 3. Conventions Visual Cue Meaning Bold Type with Initial Command names, dialog box titles, checkbox options, and dialog box options are Capital Letters shown in bold, initial capital letters. -
Page 7: Table Of Contents
Table of Contents About this Manual ............................iii How to Find Information......................iii How to Contact Altera ........................iv Typographic Conventions ......................v Board Components ............................9 Features ............................. 9 General Description ......................... 9 Default Reference Design ....................... 9 Restoring the Default Reference Design to the Board ............10 Block Diagram ........................ - Page 8 Table of Contents Nios Development Board Reference Manual, Cyclone Edition Power-Supply Circuitry ........................ 35 Clock Circuitry ..........................35 JTAG Connections ......................... 36 JTAG to Cyclone Device (J24) ....................36 JTAG to MAX Device (J5) ..................... 38 Appendix A: Shared Bus Table ......................39...
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Page 9: Board Components
The Nios development board comes pre-programmed with a 32-bit Nios processor reference design. Hardware designers can use the reference design as an example of how to use the features of the Nios development board. Software designers can use the pre-programmed Nios processor design on the board to begin prototyping software immediately. -
Page 10: Restoring The Default Reference Design To The Board
Download methods include a serial cable, a JTAG download cable, or an Ethernet cable. The GERMS monitor, an Altera- provided monitor program for the Nios processor, is running on the Console RS-232 serial port (J19). Simultaneously, a web server program is running via the ethernet connection. -
Page 11: Block Diagram
Nios Development Board Reference Manual, Cyclone Edition Board Components Block Diagram Figure 1 shows a block diagram of the board. Figure 1. Nios Development Board, Cyclone Edition Block Diagram 50MHz Oscillator 16 Mbyte SDRAM Serial Configuration Device Vccint (1.5 V) 5.0 V Regulators... -
Page 12: Nios Development Board Components
Board A complete set of schematics, a physical layout database, and GERBER Components files for the Nios development board are installed in the documents directory for the Nios development kit. Figure 2. Nios Development Board Components Altera Corporation... -
Page 13: The Cyclone Ep1C20 Device
U5 is an 8 Mbyte AMD AM29LV065D flash memory device connected to the Cyclone device and can be used for two purposes: Device A Nios embedded processor implemented on the Cyclone device can use the flash memory as general-purpose readable memory and non- volatile storage. -
Page 14: Compact Flash Connector
Nios Development Board Reference Manual, Cyclone Edition Hardware configuration data that implements the Nios reference design is pre-stored in this flash memory. The pre-loaded Nios reference design, once loaded, can identify the 8 Mbyte flash memory in its address space... - Page 15 Nios Development Board Reference Manual, Cyclone Edition Board Components Table 5 below provides compact flash pin out details Table 5. Compact Flash (CON3) Pin Table (Part 1 of 2) Cyclone Device Compact Flash Pin Compact Flash Function Pin (U60) (CON3)
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Page 16: Sdram Device
The SDRAM device pins are connected to the Cyclone device (see Table An SDRAM controller peripheral is included with the Nios development kit, allowing a Nios processor to view the SDRAM device as a large, linearly addressable memory. Table 6. SDRAM (U57) Pin Table (Part 1 of 3) - Page 17 Nios Development Board Reference Manual, Cyclone Edition Board Components Table 6. SDRAM (U57) Pin Table (Part 2 of 3) Pin Name Pin Number Connects to Cyclone Pin DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22...
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Page 18: Dual Sram Devices
SDRAM information. Dual SRAM U35 and U36 are two (512 Kbyte x 16-bit) asynchronous SRAM devices. They are connected to the Cyclone device so they can be used by a Nios Devices embedded processor as general-purpose memory. The two 16-bit devices can be used in parallel to implement a 32-bit wide memory subsystem. -
Page 19: Ethernet Mac/Phy
(for example) as an interface to a special-function daughter card. See the Altera web site for a list of available expansion daughter cards that can be used with the Nios development board at www.altera.com/devkits. - Page 20 Board Components Nios Development Board Reference Manual, Cyclone Edition Figure Figure 6 on page 20 Figure 7 on page 21 show connections from the PROTO1 expansion headers to the Cyclone device. Unless otherwise noted, labels indicate Cyclone device pin numbers.
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Page 21: Expansion Prototype Connector (Proto2)
One regulated 5-V power-supply pin (1A total max load for both PROTO1 & PROTO2) ■ Numerous ground connections The output logic level on the expansion prototype connector pins is 3.3V. The power supply included wit the Nios development kit cannot supply the maximum load current specified above. Altera Corporation... - Page 22 Board Components Nios Development Board Reference Manual, Cyclone Edition Figure 8 on page Figure 9 on page 22 Figure 10 on page 23 show connections from the PROTO2 expansion headers to the Cyclone device. Unless otherwise noted, labels indicate Cyclone device pin numbers.
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Page 23: Mictor Connector
Most Mictor connector pins on J25 connect to I/O pins on the Cyclone device (U60). For systems that do not use the Mictor connector for the Nios OCI debug module, any on-chip signals can be routed to I/O pins and probed at J25 via a Mictor cable. External scopes and logic analyzers can connect to J25 and analyze a large number of signals simultaneously. - Page 24 Nios Development Board Reference Manual, Cyclone Edition Figure 11 on page 24 shows an example of an in-target system analyzer ISA-NIOS/T (sold separately) by First Silicon Solutions (FS2) Inc. For details see www.fs2.com. Figure 11. Mictor Debug Port to OCI Debug Module Five of the signals connect directly to the JTAG pins on the Cyclone device (U60), and also connect directly to the Cyclone device’s JTAG connector...
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Page 25: Serial Port Connectors
Cyclone device cannot interface to RS-232 voltage levels directly. The Nios development board provides two serial connectors, one labeled Console and the other labeled Debug. Many processor systems make use of multiple UART communication channels during prototype and debug stages. -
Page 26: Dual 7-Segment Display
Figure 16 Cyclone device pin out details. Display Figure 16. Dual-7-Segment Display The pre-loaded Nios reference design includes parallel input/output (PIO) registers and logic for driving this display. Push-Button SW0 – SW3 are momentary-contact push-button switches that provide stimulus to designs in the Cyclone device. See Figure 17 on page 27. -
Page 27: Individual Leds
Hardware designers will never need the Connector serial flash connector for using the reference designs that came with the Nios development kit. The reference designs allow the designer to access data from the serial configuration device without using this connector. See “Cyclone Configuration” on page... -
Page 28: Configuration Controller Device (Epm7128Ae)
Board Components Nios Development Board Reference Manual, Cyclone Edition Configuration The configuration controller (U3), is an Altera EPM7128AE device. It comes pre-programmed with logic for managing board reset conditions Controller and configuring the Cyclone device from data stored in flash memory and the EPCS4 serial configuration device. -
Page 29: Configuration Data
(U5). New hexout files can be stored in the flash memory (U5) by software running on a Nios embedded processor. The Nios pre-loaded reference design includes facilities for downloading hexout files from a host (such as desktop workstation) into flash memory. -
Page 30: Safe And User Configurations
Nios Embedded Processor Software Development Reference Manual detailed information about downloading and relocating files using the GERMS monitor. Using Conventional Flash Memory The Nios Development Board includes an 8 MByte flash memory device (U5). See Table 9. It is divided into 128 individually-erasable 64K sectors. - Page 31 Nios Development Board Reference Manual, Cyclone Edition Board Components Each of the upper four (4) MBbytes of flash memory are used by either the configuration controller or the web server. Your application software may safely use the lower half (4 MBytes) of flash memory without interfering with FPGA configuration or web-server operation.
- Page 32 Board Components Nios Development Board Reference Manual, Cyclone Edition Safe Hardware Image If there is no valid User Hardware Image, or if SW9 (Force Safe) is pressed, the configuration controller begins reading data out of flash at address 0x700000. Any FPGA configuration data stored at this location is conventionally called the Safe Hardware Image.
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Page 33: The Configuration-Status Leds
This LED turns on when the safe configuration is being transferred from flash memory and stays illuminated if the safe configuration was successfully loaded into the Cyclone device. Configuration and Reset Buttons The Nios development board uses dedicated switches SW8, SW9 and SW10 for the following fixed functions: Altera Corporation... -
Page 34: Sw8 - Cpu Reset
DEV_CLRn pin (and user I/O C_4). The result of pressing SW8 depends on how the Cyclone device is currently configured. The pre-loaded Nios reference design treats SW8 as a CPU-reset pin (see Figure 19). The reference Nios CPU will reset and start executing code from its reset address when SW8 is pressed. -
Page 35: Power-Supply Circuitry
Nios Development Board Reference Manual, Cyclone Edition Board Components Power-Supply The Nios development board runs from a 9-V, unregulated, center- negative input power supply. On-board circuitry generates 5-V, 3.3-V, Circuitry and 1.5-V regulated power levels. ■ The 5-V supply is present on pin 2 of J12 and J15 for use by any device plugged into the PROTO1 or PROTO2 expansion connectors. -
Page 36: Jtag Connections
Cyclone device with a new hardware image via an Altera ByteBlaster II download cable as shown in Figure 23 on page In addition, Nios embedded processor debugger software can access the Nios OCI debug module via a download cable connected to the J24 JTAG connector. Altera Corporation... - Page 37 Nios Development Board Reference Manual, Cyclone Edition Board Components Figure 22. JTAG Connector (J24) to Cyclone Device To Mictor Connector (J25) JTAG signals JTAG Connector Cyclone Device (J24) (U53) TRST Figure 23. JTAG Connection to Download Cable Pin 1 The Cyclone device’s JTAG pins can also be accessed via the Mictor connector (J25).
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Page 38: Jtag To Max Device (J5)
Figure 24. Altera Quartus II software can perform in-system programming (ISP) to reprogram the MAX device (U3) with a new hardware configuration via an Altera ByteBlaster II download cable. Figure 24. JTAG Connector (J5) to MAX Device Pin 1 Altera Corporation... -
Page 39: Appendix A: Shared Bus Table
On the Nios Development Board, Cyclone Edition, the flash memory, SRAM and Ethernet MAC/PHY devices share address and control lines. These shared lines are referred to as the Shared Bus. Using SOPC Builder, designers can interface a Nios processor system to any device connected to the off-chip shared bus. - Page 40 Shared Bus Table Nios Development Board Reference Manual, Cyclone Edition Table 12. Shared Bus Table (Part 1 of 3) NET Name PLD (U60) Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4) Description Pin # Pin # Pin # Pin # Pin Name...
- Page 41 Nios Development Board Reference Manual, Cyclone Edition Shared Bus Table Table 12. Shared Bus Table (Part 2 of 3) NET Name PLD (U60) Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4) Description FSE_D0 Shared Data FSE_D1 FSE_D2 FSE_D3 FSE_D4 FSE_D5...
- Page 42 Shared Bus Table Nios Development Board Reference Manual, Cyclone Edition Table 12. Shared Bus Table (Part 3 of 3) NET Name PLD (U60) Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4) Description FLASH_CS_n Chip Select CE_n FLASH_OE-N Read Enable OE_n...
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Page 43: Appendix B: Restore The Factory Configuration
Appendix B: Restore the Factory Configuration The Nios development board can always be restored to its factory- programmed configuration. To restore the factory configuration, you must reprogram the flash memory on the Nios development board. Reprogramming the flash memory requires the following: ■... -
Page 44: Reprogramming The Flash Memory
Restore the Factory Configuration Nios Development Board Reference Manual, Cyclone Edition Reprogramming You can now use the Nios processor in the Cyclone device and the GERMS monitor to reprogram the flash memory by performing the the Flash following steps: Memory Connect the Console RS-232 serial connector to the host computer using a serial cable. -
Page 45: Appendix C: Board Ethernet Connection
The web server responds to any HTTP requests, regardless of origin, that arrive on its Ethernet connection. This section assumes that you are familiar with the Nios SDK shell, the nios-run utility for serial communication with the Nios development board, and the GERMS monitor. -
Page 46: Connecting The Lcd Display
Nios Development Board Reference Manual, Cyclone Edition Figure 25. Point-to-Point Connection LAN Connection — To use your Nios development board on a LAN (for example, connecting to an Ethernet hub) do the following: Connect one end of the RJ45 cable to the Ethernet connector on the development board (RJ1). -
Page 47: Ip Addresses For Point-To-Point Connections
Nios Development Board Reference Manual, Cyclone Edition Board Ethernet Connection The board will continue to attempt DHCP self-configuration for one full minute. You can tell whether DHCP has succeeded, or is still in progress, by reading status-messages on the LCD display. If your LAN does not support DHCP, or if you are using the point-to-point option above, then DHCP configuration will ultimately fail. -
Page 48: Ip Addresses For Lan Connections
Board Ethernet Connection Nios Development Board Reference Manual, Cyclone Edition IP Addresses for LAN Connections If your LAN does not support DHCP, or if DHCP self configuration failed, then you will need to assign your board a fixed IP address before you can access it over a network. -
Page 49: Index
Reset distribution 28 Safe and user configurations 30 JTAG connections 36 Starting configuration 28 JTAG to Cyclone device (J24) 36 Configuration-status LEDs JTAG to MAX device (J5) 38 Indicators 33 Conventional flash memory usage 30 Cyclone EP1C20 device 13 Altera Corporation... - Page 50 Index Nios Development Board Reference Manual, Cyclone Edition Mictor connector 23 Debug port to OCI debug module 24 J25 pin information 25 Power-supply circuitry 35 Push-button switches 26 pin information 26 Reference design default 9 restoring 10 Restore factory configuration...