Serial Connector (J19) - Altera Nios Cyclone II Edition Reference Manual

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Serial Connector
(J19)
Altera Corporation
May 2007
Table 2–9. Ethernet MAC/PHY Pin Table (Continued)
FPGA Pin U4 Pin
A9 70
C10 69
D10 68
B10 66
A10 65
E12 64
D12 63
J13 61
J14 60
F12 59
G12 58
J10 56
J11 55
C11 54
B11 53
C12 51
B12 50
D6 49
G11 48
Note to Table 2–9:
(1) Nets fe_a0 and fe_a16 to fe_a23 do not connect to U4.
See www.smsc.com for detailed information about the LAN91C111
device.
J19 is a standard DB-9 serial connector, and is typically used for
communication between the FPGA and a host computer via an RS-232
serial cable. Level-shifting buffer (U52) is used between J19 and the
FPGA, because the FPGA device cannot interface to RS-232 voltage levels
directly.
J19 is able to transmit all RS-232 signals. Alternately, the FPGA design can
use only the signals it needs, such as J19's RXD and TXD pins. LEDs are
connected to the RXD and TXD signals and visually indicate when data
is being transmitted or received.
connections between the serial connectors and the FPGA.
Reference Manual
Pin Function
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Figure 6 and Table 2–10
Nios Development Board Cyclone II Edition
Board Components
Board Net Name (1)
fe_d13
fe_d14
fe_d15
fe_d16
fe_d17
fe_d18
fe_d19
fe_d20
fe_d21
fe_d22
fe_d23
fe_d24
fe_d25
fe_d26
fe_d27
fe_d28
fe_d29
fe_d30
fe_d31
show the pin
2–15