Related Manuals for Altera 40GBASE-KR4
Summary of Contents for Altera 40GBASE-KR4
- Page 1 Ethernet Reference Design Quick User guide Example on 40GBASE-KR4 Stratix V GX Signal Integrity Development Board Date: 05/03/2016 Revision: 1.0...
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Page 2: Table Of Contents
Contents Introduction ..............................3 System Overview and Functional Description ....................4 40GBASE-KR4 Ethernet MAC and PHY IP ...................... 5 40Gbps Ethernet MAC and PHY IP Overview ....................6 Quick Start Guide ............................7 Signal Integrity Stratix V GT Edition Setup ....................9 Compile, Build, Load and Run the Software ..................... -
Page 3: Introduction
Auto-Negotiation (AN) as defined in Clause 63 (only negotiation to 40GBASE-KR4 mode is supported. The 40GBASE-KR4 PMD as defined in Clause 84 which includes Link Training (LT) as defined in Clause 72. Forward Error Correction (FEC) as defined in Clause 74. -
Page 4: System Overview And Functional Description
System Overview and Functional Description The hardware platform consists of three sub-systems: The 40GBase-KR4 MAC and PHY IP Packet Client with random packet generator and monitor System Console for configuration and control of the system This system can be represented by the following diagram:... -
Page 5: 40Gbase-Kr4 Ethernet Mac And Phy Ip
40GBASE-KR4 Ethernet MAC and PHY IP The Altera 40G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 802.3ba 2010 Higher Speed Ethernet Standard. It is including Auto-Negotiation (AN), Link Training (LT) and Forward Error Correction (FEC). This module handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 40GbE Ethernet PCS and PMA (PHY). -
Page 6: 40Gbps Ethernet Mac And Phy Ip Overview
Figure 2 Ethernet MAC and PHY IP Additional Functional Details of 40GE Ethernet IP Core: The additional details of the IP core can be found in the User guide. The IP core evaluation package and the user guide can be downloaded from Altera website: http://www.altera.com/products/ip/iup/ethernet/m-alt-40-100gb-ethernet.html... -
Page 7: Quick Start Guide
Quick Start Guide The reference design setup essentially consists of software and hardware. Software Requirement: Quartus Prime 15.1 or above (with system console feature) Transceiver Signal Integrity Development Kit – Stratix V GX Edition v12.0.0 or above (with clock control feature) [if the software says current active Quartus version isn’t the correct version then the board is broken, you need to switch to another board.] Hardware Requirement:... - Page 8 The relevant setups for each of these components are provided in detail as shown below: Figure 3 Hardware Setup The Signal Integrity Stratix V GT development board requires minimum hardware setup. Switch 6 (SW6), all 4 pin need to set to logic 0 (close). See below. Figure 4 Hardware Switches...
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Page 9: Signal Integrity Stratix V Gt Edition Setup
Signal Integrity Stratix V GT Edition Setup Open Integrity Stratix V GT development kit – Stratix V GX Edition v12.0.0 from Window “Start” manual “All Program” -> “Altera” -> “Transceiver Signal Integrity Development Kit – Stratix V GX Edition v12.0.0” -> “Clock Control”... - Page 10 Figure 6 Transceiver Bank...
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Page 11: Viewing The Result
Viewing the Result Connect the cables to the corresponding pinouts. (Note that cables should be in orders of negative and positive) Run the main_run.tcl under system_console folder in system console and go to KR4_Status tab, change KR4 Settings by reading and writing registers. Figure 7 System Console Interface Figure 8 KR4 Settings... - Page 12 You need to reset SEQ and write register and uncheck reset SEQ and rewrite register until all registers are as the below picture. Click on “Read all Register” and you can access the register values. Figure 9 KR4 Status Register The example capture is a TX to RX loopback test setting.
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Page 13: System Monitor Panel
Register 0xC0: Bit[0] : 0 = Disable the KR4 AN function. Register 0xB0: Bit[0] : 1 = Force Negotiate to FEC mode set. Bit[6:4] : 000 = no force. Bit[19] : 1 = Force Negotiate to FEC mode. Note: All change will effect only after “Reset SEQ” bit is set. Note: For normal two device setup, register 0xB0 and 0xC0 don’t need to change. -
Page 14: System Control Panel
System Control Panel There are three major functions in the system control panel, Soft Reset, Serial/parallel loopback, and PRBs testing function. The current test doesn’t need to use those functions. See capture below. Figure 11 System Control Panel Packet Monitor Panel This hardware demo design only able to generate randomize size packet. - Page 15 Note: For this TX to RX loopback test, checking the TX packet count and RX packet count is one of the methods to confirm the test pass or fail. If all TX counter are equal to RX counter, that means pass. Otherwise it could be a hardware issue.
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Page 16: Possible Issues
Possible Issues In the previous update, one lane of signal didn’t work because one of the hardware pin wasn’t transmitting data. To resolve the problem, check pin assignments and try to use alternative pins in the same transceiver bank. Quartus strictly requires TX/RX to use compatible pins, so user might need to try multiple pairs to find the right pair. -
Page 17: Reference Documents
Reference Documents Altera 40 and 100Gbps Ethernet MAC and PHY MegaCore Function User Guide https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_40_100gbe.pdf Signal Integrity Development Kit, Stratix V GT Edition Board https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-sv-gt-si.html Altera Wiki, 40G Base-KR4 Ethernet Hardware Demo http://www.alterawiki.com/wiki/40G_Base-KR4_Ethernet_Hardware_Demo#Introduction...