Altera Nios Cyclone II Edition Reference Manual page 22

Board Components
f
2–10
Nios Development Board Cyclone II Edition
Table 2–7. DDR SDRAM Pin Table (Continued)
FPGA Pin U63 Pin
V5 63
V6 65
P3 16
W4 51
U2 20
AA1 47
T6 29
V2 30
R8 31
W3 32
R5 35
U10 36
P4 37
V1 38
T9 39
T8 40
AA2 28
T10 41
U3 42
U9 26
Y4 27
U1 22
R7 44
Y3 24
V4 23
U4 21
AA6 46
AA7 45
See www.micron.com for detailed information.
Reference Manual
Board Net Name
sdram_dq14
sdram_dq15
sdram_dqs0
sdram_dqs1
sdram_dm0
sdram_dm1
sdram_a0
sdram_a1
sdram_a2
sdram_a3
sdram_a4
sdram_a5
sdram_a6
sdram_a7
sdram_a8
sdram_a9
sdram_a10
sdram_a11
sdram_a12
sdram_ba0
sdram_ba1
sdram_cas_n
sdram_cke
sdram_cs_n
sdram_ras_n
sdram_we_n
sdram_clk_n
sdram_clk_p
Altera Corporation
May 2007