Altera Nios Cyclone II Edition Reference Manual page 24

Board Components
f
2–12
Nios Development Board Cyclone II Edition
Table 2–8. Flash Memory Pin Table (Continued)
FPGA Pin
E15 4
H15 3
H16 54
A17 19
B17 18
G15 11
F15 12
F16 15
G16 2
D8 35
C8 37
F10 39
G10 41
D9 44
C9 46
B8 48
A8 50
H17 32
F17 34
G17 13
B18 16
C17 53
D17 17
Note to Table 2–8:
(1) BYTE_n on U5 is pulled low to keep the flash memory in byte
mode which restricts the usable modes of operation.
The on-board configuration controller makes assumptions about what-
resides-where in flash memory. For details refer to
Config" on page 2–35.
See www.amd.com for detailed information about the flash memory
device.
Reference Manual
U5 Pin Board Net Name
fe_a15
fe_a16
fe_a17
fe_a18
fe_a19
fe_a20
fe_a21
fe_a22
fe_a23
fe_d0
fe_d1
fe_d2
fe_d3
fe_d4
fe_d5
fe_d6
fe_d7
flash_cs_n
flash_oe_n
flash_rw_n
flash_wp_n
flash_byte_n
flash_ry_by_n
(1)
"SW10 – Reset,
Altera Corporation
May 2007