Altera Nios Cyclone II Edition Reference Manual page 26

Board Components
2–14
Nios Development Board Cyclone II Edition
Table 2–9. Ethernet MAC/PHY Pin Table (Continued)
FPGA Pin U4 Pin
C25 94
C24 95
D26 96
D25 97
E20 31
D16 32
H8 78
D11 79
E8 80
B14 81
A14 82
F14 83
G14 84
F13 85
G13 86
C15 87
B15 88
B16 89
C16 90
D15 91
E15 92
D8 107
C8 106
F10 105
G10 104
D9 102
C9 101
B8 100
A8 99
H11 76
H12 75
F11 74
E10 73
B9 71
Reference Manual
Pin Function
Byte Enable 0
Byte Enable 1
Byte Enable 2
Byte Enable 3
Read
Write
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Board Net Name (1)
enet_be_n0
enet_be_n1
enet_be_n2
enet_be_n3
enet_ior_n
enet_iow_n
fe_a1
fe_a2
fe_a3
fe_a4
fe_a5
fe_a6
fe_a7
fe_a8
fe_a9
fe_a10
fe_a11
fe_a12
fe_a13
fe_a14
fe_a15
fe_d0
fe_d1
fe_d2
fe_d3
fe_d4
fe_d5
fe_d6
fe_d7
fe_d8
fe_d9
fe_d10
fe_d11
fe_d12
Altera Corporation
May 2007