Altera Nios Cyclone II Edition Reference Manual page 29

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Altera Corporation
May 2007
■
A buffered, zero-skew copy of the on-board oscillator output from
U2.
■
A buffered, zero-skew copy of the FPGA phase-locked loop (PLL)
output.
■
A logic-negative power-on reset signal.
■
Five regulated 3.3V power-supply pins (2A total max load for both
PROTO1 & PROTO2).
■
One regulated 5V power-supply pin (1A total max load for both
PROTO1 & PROTO2).
■
Numerous ground connections.
The PROTO1 expansion prototype connector shares FPGA I/O pins with
the CompactFlash connector (CON3). Designs can use either the PROTO1
connector or the CompactFlash connector.
1
Do not connect cards to PROTO1 and CON3 at the same time.
Damage to one or both cards might result.
See the Altera web site for a list of available expansion daughter cards
that can be used with the Nios development board at
www.altera.com/devkits.
Table 2–11, Figure 2–6
PROTO1 expansion headers to the FPGA. Unless otherwise noted, labels
indicate FPGA pin numbers...
Table 2–11. PROTO1 Pin Table
FPGA Pin PROTO1 Pin
J11
U3 pin 56 1
E25 3
F24 4
F23 5
J21 6
J20 7
F25 8
F26 9
N18 10
P18 11
G23 12
G24 13
Reference Manual
and Figure 2–7 show connections from the
Connector
J11
J11
J11
J11
J11
J11
J11
J11
J11
J11
J11
J11
Nios Development Board Cyclone II Edition
Board Components
Board Net Name
proto1_RESET_n
proto1_io0
proto1_io1
proto1_io2
proto1_io3
proto1_io4
proto1_io5
proto1_io6
proto1_io7
proto1_io8
proto1_io9
proto1_io10
2–17