Test Points (Tp1 - Tp8) - Altera Nios Cyclone II Edition Reference Manual

Test Points
(TP1 – TP8)
Altera Corporation
May 2007
Table 2–16 shows the pin out information for J25. Unless otherwise noted,
labels indicate FPGA pin numbers.
Table 2–16. Mictor Connector Pin Table
FPGA Pin
V21 5
AC8 38
AD8 36
W10 34
Y10 32
V10 30
V9 28
AD6 26
AD7 24
AE5 22
AF5 20
AD4 18
AD5 16
AC5 10
AC6 8
AF4 37
AE4 35
B21 33
B22 31
A22 29
A23 27
B23 25
D21 23
C21 13
C22 9
C23 7
B25 6
TP1 – TP8 are test points connected to I/O pins on the FPGA. FPGA
designs can route signals to these I/O pins to be probed. TP1 –TP8 also
connect to the configuration controller (U3).
Reference Manual
J25 Pin Board Net Name
mictor_clk
mictor0
mictor1
mictor2
mictor3
mictor4
mictor5
mictor6
mictor7
mictor8
mictor9
mictor10
mictor11
mictor12
mictor13
mictor14
mictor15
mictor16
mictor17
mictor18
mictor19
mictor20
mictor21
mictor22
mictor23
mictor24
mictor_trclk
Nios Development Board Cyclone II Edition
Board Components
2–31