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Altera MAX 10 User Manual

Altera MAX 10 User Manual

Clocking and pll
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MAX 10 Clocking and PLL User Guide
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101 Innovation Drive
UG-M10CLKPLL
2015.06.12
San Jose, CA 95134
www.altera.com

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  • Page 1 MAX 10 Clocking and PLL User Guide 101 Innovation Drive UG-M10CLKPLL Subscribe 2015.06.12 San Jose, CA 95134 Send Feedback www.altera.com...

  • Page 2: Table Of Contents

    MAX 10 Clocking and PLL Overview..............1-1 Clock Networks Overview.......................... 1-1 Internal Oscillator Overview........................1-1 PLLs Overview..............................1-1 MAX 10 Clocking and PLL Architecture and Features........2-1 Clock Networks Architecture and Features..................... 2-1 Global Clock Networks........................2-1 Clock Pins Introduction........................2-1 Clock Resources..........................2-2 Global Clock Network Sources......................
  • Page 3 MAX 10 Clocking and PLL Implementation Guides......... 4-1 ALTCLKCTRL IP Core..........................4-1 IP Catalog and Parameter Editor....................4-1 Specifying IP Core Parameters and Options................4-2 Files Generated for Altera IP Cores (Legacy Parameter Editor)..........4-4 ALTPLL IP Core............................4-5 IP Catalog and Parameter Editor....................4-6 Specifying IP Core Parameters and Options................4-7 Files Generated for Altera IP Cores (Legacy Parameter Editor)..........
  • Page 4 TOC-4 Internal Oscillator IP Core References...............8-1 Internal Oscillator Parameters........................8-1 Internal Oscillator Ports and Signals......................8-1 Additonal Information for MAX 10 Clocking and PLL User Guide....A-1 Document Revision History for MAX 10 Clocking and PLL User Guide.......... A-1 Altera Corporation...

  • Page 5: Max 10 Clocking And Pll Overview

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 6 UG-M10CLKPLL PLLs Overview 2015.06.12 • PLL cascading • Reference clock switchover • Drive the analog-to-digital converter (ADC) clock MAX 10 Clocking and PLL Overview Altera Corporation Send Feedback...

  • Page 7: Max 10 Clocking And Pll Architecture And Features

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 8: Clock Resources

    For more information about the clock input pins connections, refer to the pin connection guidelines. Related Information MAX 10 FPGA Device Family Pin Connection Guidelines Global Clock Network Sources Table 2-2: MAX 10 Clock Pins Connectivity to the GCLK Networks GCLK CLK0p GCLK[0,2,4]...
  • Page 9 GCLK[15,18] DPCLK0 GCLK[0,2] DPCLK1 GCLK[1,3,4] DPCLK2 GCLK[5,7] DPCLK3 GCLK[6,8,9] Figure 2-1: GCLK Network Sources for 10M02, 10M04, and 10M08 Devices DPCLK2 DPCLK3 GCLK[0..4] GCLK[5..9] CLK[0,1][p,n] CLK[2,3][p,n] DPCLK0 DPCLK1 MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...

  • Page 10: Global Clock Control Block

    Dedicated clock input pins Dedicated clock input pins can drive clocks or global signals, such as synchronous and asynchro‐ nous clears, presets, or clock enables onto given GCLKs. MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...
  • Page 11 (4) You can use internal logic to enable or disable the GCLK in user mode. Each MAX 10 device has a maximum of 20 clock control blocks. There are five clock control blocks on each side of the device.

  • Page 12: Global Clock Network Power Down

    5-2 Global Clock Network Power Down You can disable the MAX 10 GCLK (power down) by using both static and dynamic approaches. In the static approach, configuration bits are set in the configuration file generated by the Quartus II software, ®...

  • Page 13: Clock Enable Signals

    PLL resynchronization. MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...

  • Page 14: Internal Oscillator Architecture And Features

    5-2 Internal Oscillator Architecture and Features MAX 10 devices have built-in internal ring oscillator with clock multiplexers and dividers. The internal ring oscillator operates up to 232 MHz which is not accessible. This operating frequency further divides down to slower frequencies.
  • Page 15 I/O buffers. These internal delays are fixed. PLL Outputs The MAX 10 PLL supports up to 5 GCLK outputs and 1 dedicated external clock output. The output frequency, f , to the GCLK network or dedicated external clock output is determined using the...

  • Page 16: Pll Features

    The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the MAX 10 device family can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
  • Page 17 PLL 2 (2) PLL 1 (1) Bank 3 Bank 4 Notes: (1) Available on all packages except V81 package. (2) Available on F256, F484, U324, and V81 packages only. MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...

  • Page 18: Clock Pin To Pll Connections

    Bank 3 Bank 4 PLL 4 (1) Note: (1) Available on all packages except E144 and U169 packages. Clock Pin to PLL Connections Table 2-5: MAX 10 Dedicated Clock Input Pin Connectivity to PLL Dedicated Clock Pin CLK[0,1][p,n] PLL1 PLL3 CLK[2,3][p,n]...

  • Page 19: Pll Control Signals

    The only time that the VCO is completely disabled is when you do not have a PLL instantiated in your design. This only applies to 10M16, 10M25, 10M40, and 10M50 devices. MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...

  • Page 20: Clock Feedback Modes

    6-6 Clock Feedback Modes The MAX 10 PLLs support up to four different clock feedback modes. Each mode allows clock multiplica‐ tion and division, phase shifting, and programmable duty cycle. The PLL fully compensates input and output delays only when you use the dedicated clock input pins associated with a given PLL as the clock sources.
  • Page 21 PFD does not pass through as much circuitry. Both the PLL internal and external clock outputs are phase-shifted with respect to the PLL clock input. MAX 10 Clocking and PLL Architecture and Features Altera Corporation...
  • Page 22 Clock at the Input pin PLL Clock at the Register Clock Port External PLL Clock Outputs Note: (1) The external clock output can lead or lag the PLL internal clock signals. MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...

  • Page 23: Pll External Clock Output

    Output Pin PLL External Clock Output Each PLL in the MAX 10 devices supports one single-ended clock output or one differential clock output. Only the output counter can feed the dedicated external clock outputs without going through the GCLK.
  • Page 24 • Differential SSTL The MAX 10 PLLs can drive out to any regular I/O pin through the GCLK. You can also use the external clock output pins as general-purpose I/O pins if you do not require any external PLL clocking.

  • Page 25: Adc Clock Input From Pll

    Instead, the input signal looks like deterministic jitter at the input of the PLL. The MAX 10 PLLs can track a spread-spectrum input clock if the input signal meets the following conditions: •...
  • Page 26 6-2 Programmable Phase Shift The MAX 10 devices use phase shift to implement clock delays. You can phase shift the output clocks from the MAX 10 PLLs using one of the following methods: • Fine resolution using VCO phase taps •...
  • Page 27 Related Information • Dynamic Phase Configuration Implementation on page 4-15 Dynamic Phase Configuration Counter Selection • on page 4-16 Dynamic Phase Configuration with Advanced Parameters • on page 4-16 MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...

  • Page 28: Clock Switchover

    The following clock switchover modes are supported in MAX 10 PLLs: • Automatic switchover—The clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to clock.
  • Page 29 ( ) that controls the multiplexer select input. clksw In this case, becomes the reference clock for the PLL. inclk1 MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...
  • Page 30 20%. This feature is useful when clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation. MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...
  • Page 31 If you do not require another switchover event, you can leave signal in a logic high state after the initial switch. Pulsing the signal high for at clkswitch clkswitch least three cycles performs another switchover event. inclk MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...

  • Page 32: Pll Cascading

    The PLLs use several divide counters and different VCO phase taps to perform frequency synthesis and phase shifts. In MAX 10 PLLs, you can reconfigure both counter settings and phase shift the PLL output clock in real time. You can also change the charge pump and loop filter components, which dynamically affects the PLL bandwidth.
  • Page 33 PLL configuration bits with the data in the scan registers. F VCO from M counter LF/K/CP from N counter scandata scanclkena configupdate inclk scandataout scandone scanclk MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...
  • Page 34 Provides more information about the ALTPLL IP core parameter settings in the Quartus II software. ALTPLL_RECONFIG Parameters • on page 7-1 Provides more information about the ALTPLL_RECONFIG IP core parameter settings in the Quartus II software. MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback...

  • Page 35: Max 10 Clocking And Pll Design Considerations

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 36: Internal Oscillator Design Considerations

    PLL Control Signals on page 2-13 Guideline: Connectivity Restrictions To comply with simultaneous switching noise (SSN) design guideline, Altera recommends that you do not use unterminated I/O in the same bank as the input clock signal to the PLL. Related Information Guidelines: Clock and Asynchronous Control Input Signal Provides more information about using I/O connectivity restrictions.

  • Page 37: Guideline: Output Clocks

    Guideline: Output Clocks Each MAX 10 PLL supports up to five output clocks. You can use the output clock port as a core output clock or an external output clock port. The core output clock feeds the FPGA core and the external output clock feeds the dedicated pins on the FPGA.

  • Page 38: Guideline: Clock Switchover

    (an over-frequency condition) in the VCO frequency. Figure 3-1: VCO Switchover Operating Frequency Primary Clock Stops Running Frequency Overshoot Switchover Occurs VCO Tracks Secondary Clock ΔF vco Related Information Clock Switchover • on page 2-22 MAX 10 Clocking and PLL Design Considerations Altera Corporation Send Feedback...

  • Page 39: Guideline: .Mif Streaming In Pll Reconfiguration

    • 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices only support streaming in single .mif image mode. Altera recommends using an external flash for dual image mode. The MAX 10 devices do not support using both dual image mode and PLL reconfiguration with simultaneously.

  • Page 40: Max 10 Clocking And Pll Implementation Guides

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 41: Specifying Ip Core Parameters And Options

    • Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation. • Click Search for Partner IP, to access partner IP information on the Altera website. Figure 4-1: Quartus II IP Catalog...
  • Page 42 Project > Add/Remove Files in you are prompted to manually add the .qsys Project to add the file. 9. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...

  • Page 43: Files Generated For Altera Ip Cores (Legacy Parameter Editor)

    UG-M10CLKPLL Files Generated for Altera IP Cores (Legacy Parameter Editor) 2015.06.12 Figure 4-2: IP Parameter Editor View IP port and parameter details Specify your IP variation name Apply preset parameters for and target device specific applications Files Generated for Altera IP Cores (Legacy Parameter Editor) The Quartus II software version generates the following output for your IP core that uses the legacy parameter editor.

  • Page 44: Altpll Ip Core

    ALTPLL IP Core The ALTPLL IP core specifies the PLL circuitry. You can use this IP core to configure the PLL types, operation modes, and advanced features of the PLL. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...

  • Page 45: Ip Catalog And Parameter Editor

    • Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation. • Click Search for Partner IP, to access partner IP information on the Altera website. MAX 10 Clocking and PLL Implementation Guides...

  • Page 46: Specifying Ip Core Parameters And Options

    3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...
  • Page 47 PLL to lose lock, but if the input clock remains within the minimum and maximum frequency specifications, the PLL is able to achieve lock. The Quartus II software shows these input MAX 10 Clocking and PLL Implementation Guides Altera Corporation...
  • Page 48 The Quartus II software prompts an error message if it is unable to implement your preferred lock range using this procedure. Therefore, you have to look into other options, such as PLL reconfiguration to support your input frequency range. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...
  • Page 49 , post-scale output areset counters, or the I , R, and C settings. 6. You can repeat steps 1 through 5 to reconfigure the PLL any number of times. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...
  • Page 50 For example, if the post-scale divide factor is 3, the high and low time count values are 2 and 1 respectively, to achieve this division. This implies a 67%–33% duty cycle. If you need a 50%–50% duty MAX 10 Clocking and PLL Implementation Guides Altera Corporation...
  • Page 51 • Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count Related Information Programmable Duty Cycle on page 2-19 Scan Chain The MAX 10 PLLs have a 144-bit scan chain. Table 4-1: PLL Component Reprogramming Bits Number of Bits Block Name Counter...
  • Page 52 • Loop filter capacitor (C) Table 4-2: Charge Pump Bit Control CP[2] CP[1] CP[0] Setting (Decimal) Table 4-3: Loop Filter Resistor Value Control LFR[4] LFR[3] LFR[2] LFR[1] LFR[0] Setting (Decimal) MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...
  • Page 53 PLL counter bypassed PLL counter not bypassed To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits are ignored. Bypass bit MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...
  • Page 54 Programmable Phase Shift on page 2-20 Dynamic Phase Configuration Parameter Settings • on page 6-4 Provides more information about the ALTPLL IP core parameter settings in the Quartus II software. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...
  • Page 55 5. On the Inputs/Lock page, turn on Create output file(s) using the ‘Advanced’ PLL Parameters. 6. Return to the PLL Reconfiguration page and turn off Create Optional Inputs for Dynamic Phase Reconfiguration. 7. Click Finish to generate the PLL instantiation file(s). MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...

  • Page 56: Files Generated For Altera Ip Cores (Legacy Parameter Editor)

    UG-M10CLKPLL 4-17 Files Generated for Altera IP Cores (Legacy Parameter Editor) 2015.06.12 When using Advanced Parameters, the PLL wrapper file (<ALTPLL_instantiation_name> <ALTPLL_instantiation_name> ) is written in a format that allows you to identify the PLL .vhd parameters. The parameters are listed in the Generic Map section of the VHDL file, or in the section of the Verilog file.

  • Page 57: Altpll_Reconfig Ip Core

    • Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation. • Click Search for Partner IP, to access partner IP information on the Altera website. MAX 10 Clocking and PLL Implementation Guides...

  • Page 58: Specifying Ip Core Parameters And Options

    3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...

  • Page 59: Files Generated For Altera Ip Cores (Legacy Parameter Editor)

    UG-M10CLKPLL 4-20 Files Generated for Altera IP Cores (Legacy Parameter Editor) 2015.06.12 • Optionally select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications. • Specify parameters defining the IP core functionality, port configurations, and device-specific features.

  • Page 60: Obtaining The Resource Utilization Report

    5. Under Fitter, expand Resource section, and select Resource Utilization by Entity to view the resource utilization information. Internal Oscillator IP Core The Internal Oscillator IP core specifies the internal oscillator frequencies for the devices. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...

  • Page 61: Ip Catalog And Parameter Editor

    • Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation. • Click Search for Partner IP, to access partner IP information on the Altera website. MAX 10 Clocking and PLL Implementation Guides...

  • Page 62: Specifying Ip Core Parameters And Options

    3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters. MAX 10 Clocking and PLL Implementation Guides Altera Corporation Send Feedback...

  • Page 63: Files Generated For Altera Ip Cores (Legacy Parameter Editor)

    UG-M10CLKPLL 4-24 Files Generated for Altera IP Cores (Legacy Parameter Editor) 2015.06.12 • Optionally select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications. • Specify parameters defining the IP core functionality, port configurations, and device-specific features.
  • Page 64 UG-M10CLKPLL 4-25 Files Generated for Altera IP Cores (Legacy Parameter Editor) 2015.06.12 Figure 4-16: IP Core Generated Files <Project Directory> <your_ip>.qip or .qsys - System or IP integration file <your_ip>.sopcinfo - Software tool-chain integration file <your_ip> - IP core variation files <your_ip>_bb.v - Verilog HDL black box EDA synthesis file...

  • Page 65: Altclkctrl Ip Core References

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 66: Altclkctrl Ports And Signals

    Clock Enable Signals on page 2-7 • Guideline: Clock Enable Signals on page 3-1 ALTCLKCTRL Ports and Signals Table 5-2: ALTCLKCTRL Input Ports for MAX 10 Devices Port Name Condition Description Optional Input that dynamically selects the clock source to drive the clkselect[] clock network that is driven by the clock buffer.
  • Page 67 Clock pins, clock outputs from the PLL, and core signals can drive the port. inclk[] Multiple clock inputs are only supported for the global clock networks. Table 5-3: ALTCLKCTRL Output Ports for MAX 10 Devices Port Name Condition Description Required Output of the clock buffer.

  • Page 68: Altpll Ip Core References

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 69: Pll Control Signals Parameter Settings

    These parameter settings create no additional top-level ports. Related Information Programmable Bandwidth • on page 2-19 • Programmable Bandwidth with Advanced Parameters on page 4-10 Charge Pump and Loop Filter • on page 4-13 ALTPLL IP Core References Altera Corporation Send Feedback...

  • Page 70: Clock Switchover Parameter Settings

    The signal goes high when the clkbad1 signal stops toggling. The signals inclk1 clkbad remain low when the input clock signals are toggling. Related Information Clock Switchover • on page 2-22 ALTPLL IP Core References Altera Corporation Send Feedback...

  • Page 71: Pll Dynamic Reconfiguration Parameter Settings

    VCO period. If the VCO frequency is at the lower end of the supported VCO range, the phase shift resolution might be larger than preferred for your design. Use this option to fine tune the phase shift step resolution. ALTPLL IP Core References Altera Corporation Send Feedback...

  • Page 72: Output Clocks Parameter Settings

    0.1°. The up and down buttons let you cycle through phase shift values. Alternatively, you can enter a number in the phase shift field manually instead of using the buttons. ALTPLL IP Core References Altera Corporation Send Feedback...

  • Page 73: Altpll Ports And Signals

    205 and 1025 respectively, the output clock frequency is calculated as 100 × 205/1025=20 MHz. The actual settings reflect the simplest fraction—the actual multiplication factor is 1, and the actual division factor is 5. ALTPLL Ports and Signals Table 6-7: ALTPLL Input Ports for MAX 10 Devices (10) Port Name Condition...
  • Page 74 Clock enable port for the serial scan chain. scanclkena Optional Contains the data for the serial scan chain. scandata (10) Replace brackets, [], in the port name with integer to get the exact name. For example, inclk0 inclk1 ALTPLL IP Core References Altera Corporation Send Feedback...
  • Page 75 UG-M10CLKPLL ALTPLL Ports and Signals 2014.12.15 Table 6-8: ALTPLL Output Ports for MAX 10 Devices (11) Port Name Condition Description Optional Specifies which clock is the primary reference clock activeclock when the clock switchover circuit initiates. If the is in use, the...
  • Page 76 PLL input clock. The maximum lock time for the PLL is provided in the MAX 10 Device Datasheet. Take the maximum lock time of the PLL and divide it by the period of the PLL input clock. The result is the number of clock cycles needed to gate the signal.
  • Page 77 UG-M10CLKPLL 6-10 ALTPLL Ports and Signals 2014.12.15 Related Information PLL Control Signals on page 2-13 ALTPLL IP Core References Altera Corporation Send Feedback...

  • Page 78: Altpll_Reconfig Ip Core References

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 79: Altpll_Reconfig Ports And Signals

    Clock input for loading individual parameters. This signal clock also clocks the PLL during reconfiguration. The clock input port must be connected to a valid clock. Refer to the MAX 10 Device Datasheet for the clock f ALTPLL_RECONFIG IP Core References Altera Corporation Send Feedback...
  • Page 80 Asynchronous reset input to the IP core. reset Altera recommends that you reset this IP core before first use to guarantee that it is in a valid state. However, it does power up in the reset state. This port must be connected.
  • Page 81 When the signal is asserted, the signal write_param busy is only asserted on the following rising edge of the clock. signal is not asserted on the same clock cycle as busy signal. write_param ALTPLL_RECONFIG IP Core References Altera Corporation Send Feedback...
  • Page 82 ALTPLL scan data output from the dynamically reconfigurable bits. The port must be pll_scandataout connected to the port of the PLL. The scandataout activity on this port can only be observed when the signal is asserted. reconfig ALTPLL_RECONFIG IP Core References Altera Corporation Send Feedback...
  • Page 83 UG-M10CLKPLL ALTPLL_RECONFIG Ports and Signals 2015.06.12 Table 7-3: ALTPLL_RECONFIG Output Ports for MAX 10 Devices Port Name Condition Description Optional Data read from the cache when is asserted. data_out[] read_param This 9-bit output bus provides the parameter data to the user.

  • Page 84: Altpll_Reconfig Counter Settings

    PLL. Any pll_scandata scandata activity on this port can only be observed when the signal is asserted. reconfig ALTPLL_RECONFIG Counter Settings Table 7-4: Settings for MAX 10 Devices counter_type[3..0] Counter Selection Binary Decimal 0000 0001 0010 CP/LF...
  • Page 85 UG-M10CLKPLL ALTPLL_RECONFIG Counter Settings 2015.06.12 Table 7-5: Settings for MAX 10 Devices counter_param[2..0] Counter Type Counter Param Binary Decimal Width (bits) High count Low count Regular counters ( Bypass Mode (odd/even division) Charge pump unused Charge pump current CP/LF Loop filter unused...

  • Page 86: Internal Oscillator Ip Core References

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 87: Document Revision History For Max 10 Clocking And Pll User Guide

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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