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Altera Stratix V Hard IP User Manual

Altera Stratix V Hard IP User Manual

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Stratix V Hard IP for PCI Express User Guide
Stratix V Hard IP for PCI Express
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document last updated for Altera Complete Design Suite version:
12.0
UG-01097-1.2
Document publication date:
June 2012
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  • Page 1 Stratix V Hard IP for PCI Express User Guide Stratix V Hard IP for PCI Express User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Document last updated for Altera Complete Design Suite version: 12.0 UG-01097-1.2 Document publication date:...
  • Page 2 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.

  • Page 3: Table Of Contents

    Customizing the Endpoint in Qsys ........... . . 2–10 Specify the Parameters for the Stratix V Hard IP for PCI Express ......2–11 Specify the Parameters for the Example Design .
  • Page 4 Single Packet Per Cycle ............. 6–26 Stratix V Hard IP for PCI Express...
  • Page 5 Altera-Defined Vendor Specific Extended Capability (VSEC) ........7–5...
  • Page 6 Revision History ..............Info–1 Stratix V Hard IP for PCI Express...
  • Page 7 How to Contact Altera ........
  • Page 8 1–viii Chapter : Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 9: Chapter 1. Datasheet

    IP implementation of PCI Express in many Altera FPGAs. Features Altera’s Stratix V Hard IP for PCI Express and the Avalon-MM Stratix V Hard IP for PCI Express IP cores support the following key features: Complete protocol stack including the Transaction, Data Link, and Physical Layers ■...
  • Page 10 12.0. The Stratix V Hard IP for PCI Express offers different features for variants that use the Avalon-ST and Avalon-MM interfaces to the Application Layer. Variants using the Avalon-ST interface offer more features; however, if you are not familiar with the PCI Express protocol, variants using the Avalon-MM interface may be easier to understand.
  • Page 11 Reordering of -out-of-order completions Not supported Supported (transparent to the Application Layer) Requests that cross 4 KByte address boundary Not supported Supported (transparent to the Application Layer) June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 12: Release Information

    The purpose of the Stratix V Hard IP for PCI Express User Guide is to explain how to use the Stratix V Hard IP for PCI Express and not to explain the PCI Express protocol.

  • Page 13: Device Family Support

    ■ Cyclone V Hard IP for PCI Express User Guide ■ Configurations The Stratix V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack including the following layers: ■ Physical (PHY) Physical Media Attachment (PMA) ■...

  • Page 14: Debug Features

    Stratix V with Hard IP for PCI Express Debug Features The Stratix V Hard IP for PCI Express includes debug features that allow observation and control of the Hard IP for faster debugging of system-level problems. For more information about debugging refer to Chapter 16, Debugging.

  • Page 15: Compatibility Testing Environment

    Random tests that test a wide range of traffic patterns Compatibility Testing Environment Altera has performed significant hardware testing of the Stratix V Hard IP for PCI Express to ensure a reliable solution. The Gen2 ×8 Endpoint passed all PCI-SIG Gold Tests and interoperability tests with a wide selection of motherboards and test equipment at the PCI-SIG Compliance Workshop #78 in December 2011.

  • Page 16: Recommended Speed Grades

    1–6: (1) This is a power-saving mode of operation. (2) Final results pending characterization by Altera for speed grades -2, -3, and -4. Refer to the .fit.rpt file generated by the Quartus II software. Stratix V Hard IP for PCI Express...
  • Page 17 1–6: (1) This is a power-saving mode of operation. (2) Final results pending characterization by Altera for speed grades -2, -3, and -4. Refer to the .fit.rpt file generated by the Quartus II software. For details on installation, refer to the Altera Software Installation and Licensing Manual.
  • Page 18 1–10 Chapter 1: Datasheet Recommended Speed Grades Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 19 Avalon-MM interface to the Application Layer. The Stratix V Hard IP for PCI Express offers exactly the same feature set in both the MegaWizard Plug-In Manager and Qsys design flows. Consequently, your choice of...
  • Page 20 2–2 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express Figure 2–1 illustrates the steps necessary to customize the Stratix V Hard IP for PCI Express and run the example design. Figure 2–1. MegaWizard Plug-In Manager and Qsys Design Flows...

  • Page 21: Megawizard Plug-In Manager Design Flow

    Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express 2–3 MegaWizard Plug-In Manager Design Flow MegaWizard Plug-In Manager Design Flow This section guides you through the steps necessary to customize the Stratix V Hard IP for PCI Express and setup the example testbench, starting with the creation of a Quartus II project.

  • Page 22: Customizing The Endpoint In The Megawizard Plug-In Manager Design Flow

    6. Specify a variation name for output files <working_dir>/example_design/<variation name>. For this walkthrough, specify <working_dir>/example_design/gen1_x8. 7. Click Next to open the parameter editor for the Stratix V Hard IP for PCI Express. 8. Specify the System Settings values in Table 2–1.
  • Page 23 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express 2–5 MegaWizard Plug-In Manager Design Flow 9. Specify the Base Address Register and Expansion ROM settings listed Table 2–2. Table 2–2. Base Address Register and Expansion ROM Settings...

  • Page 24: Understanding The Files Generated

    2–6 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express MegaWizard Plug-In Manager Design Flow 15. On the MSI Capabilities tab, for MSI messages requested, select 4. 16. On the MSI-X Capabilities tab, turn Implement MSI-X off.
  • Page 25 MegaWizard Plug-In Manager Design Flow Figure 2–2 illustrates this directory structure. Figure 2–2. Directory Structure for Stratix V Hard IP for PCI Express IP Simulation Model and Design Example <working_dir> <variant_name>.v or .vhd = gen1_x8.v, the parameterized Endpoint <variant_name>.qip = lists all files used in the Gen1 x8 Endpoint <variant_name>.bsf = gen1_x8.bsf, a block symbol file for the parameterized Endpoint...
  • Page 26 2–8 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express MegaWizard Plug-In Manager Design Flow Figure 2–3 illustrates this Qsys system. Figure 2–3. Qsys System Connecting the Endpoint Variant and Chaining DMA Testbench 4. To display the parameters of the APPS component shown in Figure 2–3, click on it...
  • Page 27 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express 2–9 MegaWizard Plug-In Manager Design Flow Figure 2–4 illustrates the GUI for the APPS component. In Figure 2–4 the block diagram shows interfaces. If you click Show signals, the block diagram expands to show all of the signals in the APPS component.

  • Page 28: Qsys Design Flow

    Modifying the Example Design Customizing the Endpoint in Qsys This section begins with the steps necessary to customize the Stratix V Hard IP for PCI Express. Because Qsys is a system design tool, this section also guides you through steps to connect the chaining DMA component testbench.

  • Page 29: Specify The Parameters For The Stratix V Hard Ip For Pci Express

    Qsys filters the component library and shows all components matching the text string you entered. 4. Click on Stratix V Hard IP for PCI Express and then click the +Add button. The parameter editor appears. The following sections provide step-by-step instructions to create the example design in Qsys.
  • Page 30 2–12 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express Qsys Design Flow 3. Under the Base and Limit Registers heading, disable both the Input/Output and Prefetchable memory options. These settings are for Root Ports. 4. Specify the Device Identification Registers listed in Table 2–10.

  • Page 31: Specify The Parameters For The Example Design

    2–13 Qsys Design Flow 13. Click the Finish button. 14. To rename the Stratix V hard IP for PCI Express, in the Name column of the System Contents tab, right-click on the component name, select Rename, and type DUT r...
  • Page 32 2–14 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express Qsys Design Flow Note that you must change the default name that Qsys provides for the exported interfaces. Figure 2–5 illustrates the exported interfaces. Figure 2–5. Qsys System Connecting the Endpoint Variant and Chaining DMA Testbench...
  • Page 33 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express 2–15 Qsys Design Flow In this example design the Avalon-ST source interface of the DUT connects to and Avalon-ST sink interface of the APPS component, and the Avalon-ST sink interface of the DUT, connects to the Avalon-ST source interface of the APPS component.

  • Page 34: Generating The Simulation Model Using Qsys

    2–16 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express Qsys Design Flow For more information about Avalon interfaces, refer to the Avalon Interface Specifications. 3. Connect the following Avalon Conduit interfaces using the technique described in Step 1.

  • Page 35: Quartus Ii Compilation

    Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express 2–17 Quartus II Compilation Table 2–15. Parameters to Specify on the Generation Tab in Qsys (Part 2 of 2) Parameter Value Synthesis Create HDL design files for synthesis Turn on this option Create block symbol file (.bsf)

  • Page 36: Compiling The Design In The Qsys Design Flow

    2–18 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express Quartus II Compilation 5. Add the Synopsys Design Constraint (SDC) shown inExample 2–1, to the top-level design file for your Quartus II project. Example 2–1. Synopsys Design Constraint create_clock -period “100 MHz”...
  • Page 37 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express 2–19 Quartus II Compilation 9. On the Family & Device Settings page, choose the following target device family and options: a. In the Family list, select Stratix V (GS/GT/GX).

  • Page 38: Modifying The Example Design

    2–20 Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express Modifying the Example Design Modifying the Example Design To use this example design as the basis of your own design, replace the Chaining DMA Example shown in Figure 2–7...
  • Page 39 ■ Transceiver reconfiguration controller In the Qsys design flow you select the Avalon-MM Stratix V Hard IP for PCI Express as a component. This component supports PCI Express ×1, ×2, ×4, or ×8 Endpoint applications with bridging logic to convert PCI Express packets to Avalon-MM transactions and vice versa.
  • Page 40 3–2 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express As this figure illustrates, this design example transfers data between an on-chip memory buffer located on the Avalon-MM side and a PCI Express memory buffer located on the root complex side.

  • Page 41: Creating A Quartus Ii Project

    Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express 3–3 Creating a Quartus II Project Creating a Quartus II Project You can create a new Quartus II project with the New Project Wizard, which helps you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity.

  • Page 42: Running Qsys

    3–4 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express Running Qsys 12. Click Finish to complete the Quartus II project. Running Qsys Follow these steps to launch the parameter editor in Qsys: 1. On the File menu, click New.
  • Page 43 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express 3–5 Customizing the Avalon-MM Stratix V Hard IP for PCI Express IP Core Table 3–2. System Settings (Part 2 of 2) Parameter Value Port type Native endpoint RX buffer credit allocation –...
  • Page 44 3–6 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express Customizing the Avalon-MM Stratix V Hard IP for PCI Express IP Core 1. Under the Device Identification Registers heading, specify the settings in Table 3–4.

  • Page 45: Adding The Remaining Components To The Qsys System

    Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express 3–7 Adding the Remaining Components to the Qsys System 3. Under the Avalon-MM System Settings heading, specify the settings in Table 3–6. Table 3–6. Avalon Memory-Mapped System Settings...
  • Page 46 3–8 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express Adding the Remaining Components to the Qsys System 3. In the DMA Controller parameter editor, specify the parameters and conditions listed in Table 3–8. Table 3–8. DMA Controller Parameters...
  • Page 47 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express 3–9 Adding the Remaining Components to the Qsys System Table 3–9. On-Chip Memory Parameters (Part 2 of 2) Parameter Value Memory initialization Initialize memory content Turn off this option...

  • Page 48: Completing The Connections In Qsys

    3–10 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express Completing the Connections in Qsys For more information about the Transceiver Reconfiguration Controller, refer to the Transceiver Reconfiguration Controller chapter in the Altera Transceiver PHY IP Core User Guide.

  • Page 49: Specifying Clocks And Address Assignments

    Base Addresses. In the design example, you assign the base addresses manually. The Avalon-MM Stratix V Hard IP for PCI Express stores the base addresses in BARs. The maximum supported size for a BAR is 4 GByte, or 32 bits.
  • Page 50 3–12 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express Specifying Address Assignments 1. In the row for the Avalon-MM slave interface base address you want to specify, click the Base column. 2. Type your preferred base address for the interface.

  • Page 51: Specifying Output Directories

    Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express 3–13 Specifying Output Directories Specifying Output Directories To generate the Qsys system, follow these steps: 1. On the Generation tab, in the Simulation section, set the following options: For Create simulation model, select Verilog.

  • Page 52: Compiling The Design

    3–14 Chapter 3: Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express Compiling the Design Compiling the Design Follow these steps to compile your design: 1. In the Quartus II software, open the pcie_top.qpf project. 2. Add <project_dir>/ep_g1_x4/synthesis/ep_ge1_x4.qip to your Quartus II project.

  • Page 53: Chapter 4. Parameter Settings

    Table 4–1: (1) The Avalon-MM Stratix V Hard IP for PCI Express does not support Root Ports in the current release. (2) The Avalon-MM Stratix V Hard IP for PCI Express supports one MSI request. You cannot change this feature.
  • Page 54 Specifies the port type. Altera recommends Native Endpoint for all new Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility. The Root Port and Legacy Endpoint are not available for the Avalon-MM Stratix V Hard IP for PCI Native Endpoint Express.
  • Page 55 This is a special power saving mode available only for Gen1 ×1 and Gen2 On/Off application clock ×1 variants. Use deprecated RX This parameter is not available for the Avalon-MM Stratix V Hard IP for Avalon-ST data byte On/Off PCI Express. enable port (rx_st_be) Enable byte parity When On, the RX and TX datapaths are parity protected.

  • Page 56: Base Address Register (Bar) And Expansion Rom Settings

    Ports. These registers are used for TLP routing and specify the address ranges assigned to components that are downstream of the Root Port or bridge. The Base and Limit registers are not available for the Avalon-MM Stratix V Hard IP for PCI Express because it does not support Root Port mode.

  • Page 57: Device Identification Registers

    3.0. Address: 0x02C. Subsystem Sets the read-only value of the Subsystem Device ID register in the 16 bits 0x0000 Device ID PCI Type 0 Configuration Space. Address: 0x02C June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 58: Pci Express And Pci Capabilities Parameters

    Device Control register. This bit is available to the Application Layer on the tl_cfg_ctl output signal as cfg_devcsr[8]. The Avalon-MM Stratix V Hard IP for PCI Express always supports 8 tags. You do not need to configure this parameter. Stratix V Hard IP for PCI Express...
  • Page 59 ■ 1111 Ranges A, B, C, and D ■ All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms. For Endpoints using PCI Express version 2.0, this option must be Implement On.

  • Page 60: Error Reporting

    Table 4–7: (1) Throughout the Stratix V Hard IP for PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in the PCI Express Base Specification Revision 2.1 or 3.0. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

  • Page 61: Msi And Msi-X Capabilities

    Table 4–6: (1) Throughout The Stratix V Hard IP for PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in the PCI Express Base Specification Revision 1.0a, 1.1, 2.0 or 2.1. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

  • Page 62: Slot Capabilities

    Refer to Section 7.8.9 of the 0–255 PCI Express Base Specification for more information. Revision 2.1 Slot number Specifies the slot number. 0-8191 Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 63: Power Management

    Maximum of 64 ns latency field of the Device Capabilities Register (0x084). Maximum of 128 n The Stratix V Hard IP for PCI Express and Avalon-MM Stratix V Hard IP for Maximum of 256 ns Endpoint L0s PCI Express do not support the L0s or L1 states. However, in a switched...

  • Page 64: Avalon Memory-Mapped System Settings

    Enabling this option allows read and write access to bridge registers.except in the Completer-Only single dword variations. Turning on this option enables the Avalon-MM Stratix V Hard IP for PCI Auto Enable PCIe Express interrupt register at power-up. Turning off this option disables the...

  • Page 65: Chapter 5. Ip Core Architecture

    June 2012 <edit Part Number variable in chapter> This chapter describes the architecture of the Stratix V Hard IP for PCI Express. The Stratix V Hard IP for PCI Express implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification 3.0.
  • Page 66 The Hard IP includes dedicated clock domain crossing logic (CDC) between the PHYMAC and Data Link Layers. This chapter provides an overview of the architecture of the Stratix V Hard IP for PCI Express. It includes the following sections: Key Interfaces ■...

  • Page 67: Key Interfaces

    Key Interfaces Key Interfaces If you select the Stratix V Hard IP for PCI Express, your design includes an Avalon-ST interface to the Application Layer. If you select the Avalon-MM Stratix V Hard IP for PCI Express, your design includes an Avalon-MM interface to the Application Layer.

  • Page 68: Avalon-Mm Interface

    Avalon-MM Interface In Qsys, the Stratix V Hard IP for PCI Express is available with either an Avalon-ST interface or an Avalon-MM interface to the Application Layer. When you select the Avalon-MM Stratix V Hard IP for PCI Express, an Avalon-MM bridge module connects the PCI Express link to the system interconnect fabric.

  • Page 69: Interrupts

    Chapter 5: IP Core Architecture 5–5 Transaction Layer Interrupts The Stratix V Hard IP for PCI Express offers three interrupt mechanisms: ■ Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request-acknowledge handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configuration Space and is programmable using Configuration Space accesses.

  • Page 70: Configuration Space

    The Configuration Space implements the following configuration registers and associated functions: Header Type 0 Configuration Space for Endpoints ■ ■ Header Type 1 Configuration Space for Root Ports Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 71: Data Link Layer

    ■ Management of the retry buffer ■ Link retraining requests in case of error through the Link Training and Status State Machine (LTSSM) of the Physical Layer June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 72 NAK DLLP reception. For ACK DLLP reception, the retry buffer discards all acknowledged packets. ■ ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequence number of transmitted packets. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 73: Physical Layer

    ACK/NAK FC DLLP (low priority) Physical Layer The Physical Layer is the lowest level of the Stratix V Hard IP for PCI Express. It is the layer closest to the link. It encodes and transmits packets across a link and accepts and decodes received packets.
  • Page 74 The Physical Layer integrates both digital and analog elements. Intel designed the PIPE interface to separate the MAC from the PHY. The Stratix V Hard IP for PCI Express compiles with the PIPE interface specification.

  • Page 75: Pci Express Avalon-Mm Bridge

    DLL. PCI Express Avalon-MM Bridge In Qsys, the Stratix V Hard IP for PCI Express is available with either an Avalon-ST or an Avalon-MM interface to the Application Layer. When you select the Avalon-MM Stratix V Hard IP for PCI Express, an Avalon-MM bridge module connects the PCI Express link to the interconnect fabric.
  • Page 76 PCI Link Tx Read Response Tx Slave Module Address Translator Avalon-MM PCI Express Rx Master Rx Controller Avalon-MM Rx Read Response Rx Master Module Rx Master Module Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 77: Avalon-Mm-To-Pci Express Write Requests

    All subsequent byte enables must be asserted until the deasserting byte enable. ■ The Avalon-MM byte enable may deassert, but only in the last qword of the burst. To improve PCI Express throughput, Altera recommends using an Avalon-MM burst master without any byte-enable restrictions. Avalon-MM-to-PCI Express Upstream Read Requests...

  • Page 78: Pci Express-To-Avalon-Mm Read Completions

    4’b1000 Write byte 3 only In burst mode, the Stratix V Hard IP for PCI Express supports only byte enable values that correspond to a contiguous data burst. For the 32-bit data width example, valid values in the first data phase are 4’b1111, 4’b1110, 4’b1100, and 4’b1000, and valid values in the final data phase of the burst are 4’b1111, 4’b0111, 4’b0011, and 4’b0001.

  • Page 79: Pci Express-To-Avalon-Mm Downstream Read Requests

    Figure 5–7. Address Translation in TX and RX Directions Qsys Generated Endpoint with DMA Controller and On-Chip RAM Avalon-MM Stratix V Hard IP for PCI Express Chip Interconnect PCI Express Avalon-MM Bridge...

  • Page 80: Avalon-Mm-To-Pci Express Address Translation

    PCI Express address before the request packet is sent to the Transaction Layer. You can specify up to 512 address pages and sizes ranging from 4 KByte to 4 GBytes when you customize your Avalon-MM Stratix V Hard IP for PCI Express as described in “Avalon to PCIe Address Translation Settings”...

  • Page 81: Completer Only Single Dword Endpoint

    The completer-only single dword endpoint supports the following requests: ■ Read and write requests of a single dword (32 bits) from the Root Complex June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 82: Rx Block

    As this figure illustrates, the completer-only single dword endpoint connects to a PCI Express root complex. A bridge component includes the Stratix V Hard IP for PCI Express TX and RX blocks, an Avalon-MM RX master, and an interrupt handler. The bridge connects to the FPGA fabric using an Avalon-MM interface.

  • Page 83: Avalon-Mm Rx Master Block

    IRQ column of Qsys. When the MSI registers in the Configuration Space of the Completer Only Single Dword Stratix V Hard IP for PCI Express are updated, there is a delay before this information is propagated to the Bridge module shown in Figure 5–9.
  • Page 84 5–20 Chapter 5: IP Core Architecture Completer Only Single Dword Endpoint Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 85: Chapter 6. Ip Core Interfaces

    June 2012 <edit Part Number variable in chapter> This chapter describes the signals that are part of the Stratix V Hard IP for PCI Express. It describes the top-level signals in the following variants: Signals in the Stratix V Hard IP for PCI Express with Avalon-ST Interface ■...
  • Page 86 Stratix V Hard IP for PCI Express using the Avalon-ST interface. Figure 6–1. Signals in the Stratix V Hard IP for PCI Express with Avalon-ST Interface Stratix V Hard IP for Express, Avalon-ST Interface...
  • Page 87 Signals Removed csrt These signals are driven by the embedded reset controller and are no longer available at the top level of the Stratix V Hard IP for PCI Express IP Core. srst June 2012 Altera Corporation Stratix V Hard IP for PCI Express...

  • Page 88: Avalon-St Rx Interface

    1 indicates that a TLP ends in rx_st_data[255:128] ■ In single packet per cycle mode, this signal is a single bit which indicates that a TLP ends in this cycle. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 89 Clocks rx_st_data into the Application Layer. Deasserts within 2 clocks of rx_st_ready deassertion and reasserts rx_st_valid valid within 2 clocks of rx_st_ready assertion if more data is available to send. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 90 When an uncorrectable ECC error is detected, rx_st_err is asserted for at least 1 cycle while rx_st_valid is asserted. Altera recommends resetting the Stratix V Hard IP for PCI Express when an uncorrectable (double-bit) ECC error is detected. Component Specific Signals The Application Layer asserts this signal to tell the Hard IP to stop sending non-posted requests.

  • Page 91: Data Alignment And Timing For The 64-Bit Avalon-St Rx Interface

    Data Alignment and Timing for the 64-Bit Avalon-ST RX Interface To facilitate the interface to 64-bit memories, the Stratix V Hard IP for PCI Express aligns data to the qword or 64 bits by default; consequently, if the header presents an address that is not qword aligned, the Hard IP block shifts the data within the qword to achieve the correct alignment.
  • Page 92 64-bit bus. In this example, the byte address is unaligned and ends with 0x4, causing the first data to correspond to rx_st_data[63:32]. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 93 Figure 6–5. 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLPs with Qword Aligned Addresses pld_clk rx_st_data[63:32] header1 header3 data1 rx_st_data[31:0] header0 header2 data0 rx_st_sop rx_st_eop rx_st_be[7:4] rx_st_be[3:0] June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 94 Figure 6–7 illustrates the timing of the RX interface when the Application Layer backpressures the Stratix V Hard IP for PCI Express by deasserting rx_st_ready. The rx_st_valid signal deasserts within three cycles after rx_st_ready is deasserted. In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is held until the Application Layer is able to accept it.

  • Page 95: Data Alignment And Timing For The 128-Bit Avalon-St Rx Interface

    Figure 6–9. 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Qword Aligned Addresses pld_clk data3 rx_st_data[127:96] header2 data2 rx_st_data[95:64] header1 data1 data<n> rx_st_data[63:32] header0 data0 data<n-1> rx_st_data[31:0] rx_st_bardec[7:0] rx_st_sop rx_st_eop rx_st_empty rx_st_valid June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 96 Header 3 Data 2 rx_st_data[127:96] Data n Header 2 Data 1 rx_st_data[95:64] Data n-1 Header 1 Data 0 rx_st_data[63:32] Data n-2 Header 0 rx_st_data[31:0] rx_st_sop rx_st_eop rx_st_empty Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 97 4562 . . . c19a . . . 000a7896c000bc34... 3458ce. . . 2457ce. . . 0217b . . . 134c . . . 8945 . . . rx_st_data[127:0] rx_st_sop rx_st_eop rx_st_empty rx_st_ready rx_st_valid June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 98: Single Packet Per Cycle

    256-bit Avalon-ST interface. Turn on Enable Multiple Packets per Cycle on the System Settings tab of the parameter editor to change multiple packets per cycle. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 99: Data Alignment And Timing For 256-Bit Avalon-St Rx Interface

    Figure 6–17. 256-Bit Avalon-ST RX Packets Use of rx_st_empty and Single-Cycle Packets pld_clk XXXXXXXXXXXXXXXX. . . 4592001487DF08876210... XX..BE ... rx_st_data[255:0] rx_st_sop rx_st_eop rx_st_empty[1:0] rx_st_ready rx_st_valid June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 100: Multiple Packets Per Cycle (256-Bit Interface Only)

    12... 12... 12... 00... 12... 12... 12... 12... 12... 12... 12... 003458 FF... FFFFFFFF FFFFFFFF rx_st_be[31:0] rx_st_sop[0] rx_st_eop[0] rx_st_sop[1] rx_st_eop[1] rx_st_ready rx_st_valid rx_st_bardec1[7:0] rx_st_bardec2[7:0] rx_st_empty[1:0] rx_st_err rx_st_mask Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 101: Avalon-St Tx Interface

    2 cycles to facilitate timing closure; however, a readyLatency of 1 cycle is possible. If no other delays are added to the read-valid latency, the resulting delay corresponds to a readyLatency of 2. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 102 Figure 6–22 on page 6–22 for the timing of this signal. To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid signals. If no other delays are added to the ready-valid latency, the resulting delay corresponds to a readyLatency of 2.
  • Page 103 [5]: posted headers ■ component tx_cred_fc_infinite [4]: posted data ■ specific [3]: non-posted header ■ [2]: non-posted data ■ [1]: completion header ■ [0]: completion data ■ June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 104: Avalon-St Packets To Pci Express Tlps

    For additional information about TLP packet headers, refer to Appendix A, Transaction Layer Packet (TLP) Header Formats and Section 2.2.1 Common Packet Header Fields in the PCI Express Base Specification 2.1. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 105: Data Alignment And Timing For The 64-Bit Avalon-St Tx Interface

    (4) Header3 = pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15}, 4 dword header only (5) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0} (6) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4} June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 106 Figure 6–22 illustrates the timing of the TX interface when the Stratix V Hard IP for PCI Express backpressures the Application Layer by deasserting tx_st_ready. Because the readyLatency is two cycles, the Application Layer deasserts tx_st_valid after two cycles and holds tx_st_data until two cycles after tx_st_ready is asserted.

  • Page 107: Data Alignment And Timing For The 128-Bit Avalon-St Tx Interface

    Data 4 tx_st_data[127:96] tx_st_data[95:64] Header 2 Data 3 Header 1 Data 2 Data (n) tx_st_data[63:32] Header 0 Data 1 Data (n-1) tx_st_data[31:0] tx_st_sop tx_st_eop tx_st_valid tx_st_empty tx_st_err June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 108 Header 3 Data 2 tx_st_data[127:96] Data n Header 2 Data 1 tx_st_data[95:64] Data n-1 Header 1 Data 0 tx_st_data[63:32] Data n-2 Header 0 tx_st_data[31:0] tx_st_sop tx_st_eop tx_st_valid tx_st_empty Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 109: Data Alignment And Timing For The 256-Bit Avalon-St Tx Interface

    Figure 6–29 illustrates the timing of the TX interface when the Stratix V Hard IP for PCI Express backpressures the Application Layer by deasserting tx_st_ready. Because the readyLatency is two cycles, the Application Layer deasserts tx_st_valid after two cycles and holds tx_st_data until two cycles after tx_st_ready is reasserted Figure 6–29.

  • Page 110: Single Packet Per Cycle

    Header 1 Header 0 Header 1 Header 0 tx_st_data[63:0] Data 0 Header 2 XXXXXXXX Header 2 tx_st_data[127:64] XXXXXXXX Data 0 XXXXXXXXX XXXXXXXX tx_st_data[191:128] XXXXXXXXX XXXXXXXX XXXXXXXXX XXXXXXXX tx_st_data[255:192] tx_st_sop tx_st_empty[1:0] Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 111: Multiple Packets Per Cycle

    ECRC data for TX data. For packets with no payload data, the ECRC position corresponds to the position of Data0 in these figures. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 112: Clock Signals

    Table 6–6. Clock Signals Hard IP Implementation Signal Description Reference clock for the Stratix V Hard IP for PCI Express. It must have the frequency specified refclk under the System Settings heading in the parameter editor. Clocks the Application Layer. You must drive this clock from coreclkout_hip.
  • Page 113 For example, if you are using the Hard IP instance in the bottom left corner of the device, you must connect pin_perst to nPERSL0. For maximum use of the Stratix V device, Altera recommends that you use the bottom left Hard IP first. This is the only location that supports CvP over a PCIe link.
  • Page 114 11001: L2.transmit.Wake ■ 11010: Speed.Recovery ■ 11011: Recovery.Equalization, Phase 0 ■ ltssmstate[4:0] (continued) 11100: Recovery.Equalization, Phase 1 ■ 11101: Recovery.Equalization, Phase 2 ■ 11110: recovery.Equalization, Phase 3 ■ Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 115: Ecc Error Signals

    If a specific location of MRAM has errors, as long as that data is in the ECC decoder, the flag indicates the error. When a correctable ECC error occurs, the Stratix V Hard IP for PCI Express recovers without any loss of information. No Application Layer intervention is required. In the case of uncorrectable ECC error, Altera recommend that you reset the core.

  • Page 116: Interrupts For Endpoints

    Device Control register. If enabled, serr_out is asserted for a single clock serr_out cycle when a system error occurs. System errors are described in the PCI Express Base Specification 2.0 in the Root Control register. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 117: Completion Side Band Signals

    Table 6–11 describes the signals that comprise the completion side band signals for the Avalon-ST interface. The Stratix V Hard IP for PCI Express provides a completion error interface that the Application Layer can use to report errors, such as programming model errors.

  • Page 118: Transaction Layer Configuration Space Signals

    Table 6–14 on page 6–37. Configuration status bits. This information updates every pld_clk cycle. Refer to Table 6–13 tl_cfg_sts[52:0] for a detailed description of the status bits. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 119 Link Status Register[15:0] Bit 12: Slot clock configuration ■ Bit 11: Link Training ■ Bit 10: Undefined ■ Bits[9:4]: Negotiated Link Width ■ Bits[3:0] Link Speed ■ June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 120: Configuration Space Register Access Timing

    Configuration Space register information is being driven onto tl_cfg_ctl. Figure 6–33. tl_cfg_ctl Timing pld_clk tl_cfg_add[3:0] 00... 00... 00... 7F... 00... 00... 00000000 00000000 tl_cfg_ctl[31:0] Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 121: Configuration Space Register Access

    Device Control for the PCI Express Table 7–7 on cfg_dev_ctrl capability structure. page 7–4 cfg_dev2ctrl[15:0] is device control 2 for the PCI Express Table 7–8 on cfg_dev_ctrl2 capability structure. page 7–5 June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 122 The upper 20 bits of the IO limit registers of the Type1 Table 7–3 on Configuration Space. This register is only available in Root Port page 7–2 cfg_io_bas mode. 0x01C Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 123 Mapping for TC1. — cfg_tcvcmap cfg_tcvcmap[8:6]: Mapping for TC2. cfg_tcvcmap[11:9]: Mapping for TC3. cfg_tcvcmap[14:12]: Mapping for TC4. cfg_tcvcmap[17:15]: Mapping for TC5. cfg_tcvcmap[20:18]: Mapping for TC6. cfg_tcvcmap[23:21]: Mapping for TC7. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 124 3’b010: 4 MSI allocated ■ [6:4] message 3’b011: 8 MSI allocated ■ enable 3’b100: 16 MSI allocated ■ 3’b101: 32 MSI allocated ■ 3’b110: Reserved ■ 3’b111: Reserved ■ Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 125: Parity Signals

    System Settings heading of the parameter editor. Parity is odd. This option is not available for the Avalon-MM Stratix V Hard IP for PCI Express. Parity protection provides some data protection in systems that do not use ECRC checking.

  • Page 126: Lmi Signals

    2’b01: A parity error was detected by the TX Data Link Layer. Altera ■ recommends resetting the Stratix V Hard IP for PCI Express when this error is tx_par_err[1:0] detected. Contact Altera if resetting becomes unworkable. 2’b10: A parity error was detected by the TX Transaction Layer. The TLP is ■...
  • Page 127 AER header logging, and debugging purposes only. In Root Port mode, do not access the Configuration Space using TLPs and the LMI bus simultaneously. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 128: Lmi Read Operation

    10-bit address and 16-bit data. You can use this bus dynamically modify the value of configuration registers that are read-only at run time. Tp ensure proper system operation, Altera recommends that you reset or repeat device enumeration of the PCI Express link after changing the value of read-only configuration registers of the Hard IP.
  • Page 129 D2 D3 3 clks avmm_rd avmm_rdata[15:0] For a detailed description of the Avalon-MM protocol, refer to the Avalon Memory-Mapped Interfaces chapter in the Avalon Interface Specifications. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 130: Power Management Signals

    Table 6–22 shows the layout of the Power Management Capabilities register. Table 6–22. Power Management Capabilities Register data rsvd PME_status data_scale data_select PME_EN rsvd PM_state register Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 131 Then, the Application Layer sends the PME_to_ack message to the Root Port by asserting pme_to_cr. Figure 6–38. pme_to_sr and pme_to_cr in an Endpoint IP core pme_to_sr hard pme_to_cr June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 132: Avalon-Mm Interface

    6–39, signals listed for rxm_bar0 are also exist for rxm_bar1 through rxm_bar5 when those BARs are enabled in the parameter editor. Figure 6–39. Signals in the Qsys Avalon-MM Stratix V Hard IP for PCI Express Avalon-MM Stratix V Hard IP for PCI Express...

  • Page 133: 32-Bit Non-Bursting Avalon-Mm Control Register Access (Cra) Slave Signals

    Table 6–24 lists the interfaces of the Avalon-MM Stratix V Hard IP for PCI Express with links to the sections that describe them. Table 6–24. Signal Groups in the Avalon-MM Stratix V Hard IP for PCI Express Variants Completer Full...

  • Page 134: Rx Avalon-Mm Master Signals

    16 individual interrupt signals (<m> ≤ 15). Note to Table 6–26: (1) <n> represents the BAR number for all signals. The core supports up to 6 BARs. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 135: 64-Bit Bursting Tx Avalon-Mm Slave Signals

    64-Bit Bursting TX Avalon-MM Slave Signals This optional Avalon-MM bursting slave port propagates requests from the interconnect fabric to the full-featured Avalon-MM Stratix V Hard IP for PCI Express. Requests from the interconnect fabric are translated into PCI Express request packets.

  • Page 136: Physical Layer Interface Signals

    Write request asserted by the system interconnect fabric to request a write. The Avalon-MM Stratix V Hard IP for PCI Express requires that the Avalon-MM master assert this signal continuously from the txs_Write first data phase through the final data phase of the burst. The Avalon-MM master Application Layer must guarantee the data can be passed to the interconnect fabric with no pauses.

  • Page 137: Transceiver Reconfiguration

    (PVT). Among the analog settings that you can reconfigure are: V , pre-emphasis, and equalization. reconfig_from_xcvr[(<n>46)-1:0] You can use the Altera Transceiver Reconfiguration Controller to reconfig_to_xcvr[(<n>70)-1:0] dynamically reconfigure analog settings in Stratix V devices. For more information about instantiating the Altera Transceiver Reconfiguration...

  • Page 138: Serial Interface Signals

    (1) The ×1 IP core only has lane 0. The ×4 IP core only has lanes 3–0. Refer to Pin-out Files for Altera Devices for pin-out tables for all Altera devices in .pdf, .txt, and .xls formats. Channel Placement for Gen1 and Gen2 Using CMU PLL Figure 6–41...
  • Page 139 Channel 2 - Data PCI Express Lane 2 PCI Express Lane 1 Channel 1 - Data Channel 0 -Data PCI Express Lane 0 CCD = Central Clock Divider June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 140 Channel 2 - Data PCI Express Lane 2 Channel 1 - Data PCI Express Lane 1 Channel 0 - Data PCI Express Lane 0 CCD = Central Clock Divider Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 141: Channel Placement For Gen1 And Gen2 Using Atx Pll

    PLL0 Channel 0 - Channel 0 - PCI Express Lane 0 PCI Express Lane 0 Data Data LCD = Local Clock Divider CCD = Central Clock Divider June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 142 Channel 2 - Data PCI Express Lane 2 PCI Express Lane 1 Channel 1 - Data Channel 0 -Data PCI Express Lane 0 CCD = Central Clock Divider Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 143: Channel Placement For Gen3 Using Both Cmu And Atx Plls

    Hard IP PIPE interface in hardware, including probing these ® signals using SignalTap II Embedded Logic Analyzer. The Gen3 simulation model supports serial only simulation with equalization bypassed. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 144 Power down <n>. This signal requests the PHY to change its power state powerdown0[1:0] to the specified state (P0, P0s, P1, or P2). Transmit de-emphasis selection. The Stratix V Hard IP for PCI Express sets the value for this signal based on the indication received from the tx_deemph0 other end of the link during the Training Sequences (TS).
  • Page 145 5’b 01000: Config.Lanenumaccept ■ 5’b01001: Config.Lanenumwait ■ 5’b01010: Config.Complete ■ 5’b 01011: Config.Idle ■ 5’b01100: Recovery.Rcvlock ■ 5’b01101: Recovery.Rcvconfig ■ 5’b01110: Recovery.Idle ■ 5’b 01111: L0 ■ June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 146: Test Signals

    Altera recommends that you use the test_out and test_in signals for debug or non-critical status monitoring purposes such as LED displays of PCIe link status. They should not be used for design function purposes. Use of these signals will make it more difficult to close timing on the design.
  • Page 147 ■ Notes to Table 6–32: (1) All signals are per lane. (2) Refer to “PIPE Interface Signals” on page 6–60 for definitions of the PIPE interface signals. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 148 6–64 Chapter 6: IP Core Interfaces Test Signals Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 149: Chapter 7. Register Descriptions

    Altera-Defined Vendor Specific Extended 0x200:0x240 Capability (VSEC) for details.) 0x300:0x318 Secondary PCI Express Extended Capability Structure (for Gen3 operation) 0x31C:7FC Reserved 0x800:0x834 Advanced error reporting (AER) (optional) 0x838:0x8FF Reserved June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 150 Device ID Vendor ID 0x004 Status Command 0x008 Class code Revision ID Primary Latency 0x00C BIST Header Type Cache Line Size Timer 0x010 BAR Registers 0x014 BAR Registers Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 151 Notes to Table 7–4: (1) Specifies the byte offset within Stratix V Hard IP for PCI Express IP core’s address space. (2) Refer to Table 7–36 on page 7–18 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express Base Specification 2.0.
  • Page 152 7–7: (1) Refer to Table 7–36 on page 7–18 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express Base Specification 2.0. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 153: Altera-Defined Vendor Specific Extended Capability (Vsec)

    Configuration via Protocol (CvP) programming and detailed internal error reporting. Table 7–9 the text in green links to the detailed register description. Table 7–9. Altera-Defined Vendor Specific Capability Structure (Part 1 of 2) Register Name Byte Offset 31:20 19:16 15:8...
  • Page 154 Bits Register Description Value Access Altera Marker. This read only register is an additional marker. If you use the standard Altera Programmer software to configure the device with CvP, this [31:0] A Device Value marker provides a value that the programming software reads to ensure that it is operating with the correct VSEC.
  • Page 155 Indicates that CvP data is treated as encrypted Variable Table 7–16 defines the fields of the CvP Mode Control register which provides global control of the CvP operation. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 156 CVP_FULLCONFIG. Request that the FPGA control block reconfigure the entire 1’b0 FPGA including the Stratix V Hard IP for PCI Express, bring the PCIe link down. HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The following encodings are defined: 1: Selects internal clock from PMA which is required for CVP_MODE ■...
  • Page 157 CvP Programming Control register. This register is written by the programming software to control CvP programming. Refer to Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide more information about using CvP. Table 7–18. CvP Programming Control Register...
  • Page 158 Reserved. When set, the retry buffer correctable ECC error status indicates an error. RW1CS When set, the RX buffer correctable ECC error status indicates an error. RW1CS Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 159: Pci Express Avalon-Mm Bridge Control Register Access Content

    Root Complex only, from Avalon-MM processors only, or from both types of processors. Because all accesses come across the interconnect fabric—requests from the Avalon-MM Stratix V Hard IP for PCI Express are routed through the interconnect fabric—hardware does not enforce restrictions to limit individual processor access to specific regions.

  • Page 160: Avalon-Mm To Pci Express Interrupt Registers

    Avalon-MM bridge logic and allow PCI Express interrupts to be asserted when enabled. Only Root Complexes should access these registers; however, hardware does not prevent other Avalon-MM masters from accessing them. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 161 Enables generation of PCI Express interrupts when a specified Avalon-MM interrupt signal is asserted. Your [15:0] AVL_IRQ[15:0] Qsys system may have as many as 16 individual input interrupt signals. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 162: Pci Express Mailbox Registers

    Avalon-MM-to-PCI Express Mailbox 3 A2P_MAILBOX3 0x0910 Avalon-MM-to-PCI Express Mailbox 4 A2P_MAILBOX4 0x0914 Avalon-MM-to-PCI Express Mailbox 5 A2P_MAILBOX5 0x0918 Avalon-MM-to-PCI Express Mailbox 6 A2P_MAILBOX6 0x091C Avalon-MM-to-PCI Express Mailbox 7 A2P_MAILBOX7 Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 163: Avalon-Mm-To-Pci Express Address Translation Table

    Memory Space, 32-bit PCI Express address. 32-bit header is generated. Address bits 63:32 of the translation table entries are ignored. Memory space, 64-bit PCI Express address. 64-bit address header is generated. Reserved. Reserved. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 164: Pci Express To Avalon-Mm Interrupt Status And Enable Registers

    Only bits implemented in the PCI Express to Avalon-MM Interrupt Enable Interrupt Status register are implemented in the Enable register. Reserved bits cannot be set to a 1. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 165: Avalon-Mm Mailbox Registers

    PCI Express-to-Avalon-MM mailbox 3 P2A_MAILBOX3 0x3B10 PCI Express-to-Avalon-MM mailbox 4 P2A_MAILBOX4 0x3B14 PCI Express-to-Avalon-MM mailbox 5 P2A_MAILBOX5 0x3B18 PCI Express-to-Avalon-MM mailbox 6 P2A_MAILBOX6 0x3B1C PCI Express-to-Avalon-MM mailbox 7 P2A_MAILBOX7 June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 166: Correspondence Between Configuration Space Registers And The Pcie Specification

    Base Address Registers (Offset 10h - 24h) 0x018 Base Address 2 Base Address Registers (Offset 10h - 24h) 0x01C Base Address 3 Base Address Registers (Offset 10h - 24h) Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 167 MSI and MSI-X Capability Structures 0x6C MSI-X Table Offset BIR MSI and MSI-X Capability Structures 0x70 Pending Bit Array (PBA) Offset BIR MSI and MSI-X Capability Structures June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 168 Root Error Command Root Error Command Register 0x830 Root Error Status Root Error Status Register Error Source Identification Register Correctable 0x834 Error Source Identification Register Error Source ID Register Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 169: Chapter 8. Reset And Clocks

    A second reset controller is implemented in hard logic. Software selects the appropriate reset controller depending on the configuration you specify. Both reset controllers reset the Stratix V Hard IP for PCI Express IP Core and provide sample reset logic in the example design.
  • Page 170 Controller Non-Sticky Registers pld_clk_inuse phy_mgmt_reset coreclkout_hip Datapath State Machines of Hard IP Core reconfig_xcvr_clk reconfig_xcvr_clk GPLL reconfig_locked free running clock or refclk if CvP is used Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 171 2. csrt and srst are released 32 cycles after pld_clk_inuse is asserted. 3. The Hard IP for PCI Express deasserts the reset_status output to the Application Layer. 4. The altpcied_<device>v_hwtcl.sv deasserts app_rstn 32 cycles after reset_status is released. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 172 3 ms. Figure 8–4 illustrates the TX transceiver reset sequence. Figure 8–4. TX Transceiver Reset Sequence npor 127 cycles pll_locked npor_serdes tx_digitalreset Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 173: Clocks

    Figure 8–5 illustrates the clock domains when using coreclkout_hip to drive the Application Layer and the pld_clk of the Stratix V Hard IP for PCI Express IP Core. Figure 8–5. Clock Domains and Clock Generation for the Application Layer Hard IP for PCI Express...

  • Page 174: P_Clk

    Gen2 250 MHz ×4 Gen2 125 MHz ×8 Gen2 250 MHz ×8 Gen2 125 MHz ×1 Gen3 125 MHz ×4 Gen3 250 MHz ×4 Gen3 125 MHz Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 175: Pld_Clk

    Application Layer clock along with the pld_clk input to the Stratix V Hard IP for PCI Express IP Core. The pld_clk can optionally be sourced by a different clock than coreclkout_hip. The pld_clk minimum frequency cannot be lower than the coreclkout_hip frequency.
  • Page 176 Avalon-MM interface for Hard IP dynamic reconfiguration 50–125 MHz interface which you can use to change the value of read-only hip_reconfig_clk configuration registers at run-time. This interface is optional. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 177: Supported Message Types

    9. Transaction Layer Protocol (TLP) Details June 2012 <edit Part Number variable in chapter> This chapter provides detailed information about the Stratix V Hard IP for PCI Express TLP handling. It includes the following sections: Supported Message Types ■ ■...
  • Page 178 Set Slot Power Receive In Root Port mode, through software. Limit Vendor-defined Messages Transmit Transmit Vendor Defined Type 0 Receive Receive Transmit Transmit Vendor Defined Type 1 Receive Receive Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 179: Transaction Layer Routing Rules

    Layer logic processes the requests and generates the read completions, if needed. ■ In Endpoint mode, received Type 0 Configuration requests from the PCI Express upstream port route to the internal Configuration Space and the Stratix V Hard IP for PCI Express generates and transmits the completion. ■...

  • Page 180: Receive Buffer Reordering

    The rx_mask signal blocks non-posted request transactions made to the Application Layer interface so that only posted and completion transactions are presented to the Application Layer. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 181 MSI requests are conveyed in exactly the same manner as PCI Express memory write requests and are indistinguishable from them in terms of flow control, ordering, and data integrity. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 182 9–6 Chapter 9: Transaction Layer Protocol (TLP) Details Receive Buffer Reordering Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 183: Chapter 10. Optional Features

    Active Serial or Active Quad Device Configuration Config Cntl Block PCIe Port PCIe Link used for Hard IP Configuration for PCIe via Protocol (CvP) Stratix V Device June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 184: Ecrc

    If the ECRC forwarding option is turned on, the ECRC value is forwarded to the Application Layer with the TLP. If the ECRC forwarding option is turned off, the ECRC value is not forwarded. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 185: Ecrc On The Tx Path

    (1) All unspecified cases are unsupported and the behavior of the Hard IP is unknown. (2) The ECRC Generation Enable field is in the Configuration Space Advanced Error Capabilities and Control Register. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 186: Lane Initialization And Reversal

    1, 2, or 4 lanes. The ×8 variant supports initialization and operation with components that have 1, 2, 4, or 8 lanes. The Stratix V Hard IP for PCI Express supports lane reversal, which permits the logical reversal of lane numbers for the ×1, ×2, ×4, and ×8 configurations. Lane reversal allows more flexibility in board layout, reducing the number of signals that must cross over each other when routing the PCB.

  • Page 187: Chapter 11. Interrupts

    Interrupts for Endpoints Using the Avalon-ST Application Interface The Stratix V Hard IP for PCI Express provides support for PCI Express legacy interrupts, MSI, and MSI-X interrupts when configured in Endpoint mode. The MSI, MSI-X, and legacy interrupts are mutually exclusive. After power up, the Hard IP block...
  • Page 188 Figure 11–2. Example Implementation of the MSI Handler Block app_int_sts Vector 0 app_int_en0 msi_enable & Master Enable app_msi_req0 app_int_sts0 app_msi_req app_msi_ack Arbitration Vector 1 app_int_en1 app_msi_req1 app_int_sts1 Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 189 Figure 11–4 illustrates the interactions among MSI interrupt signals for the Root Port Figure 11–3. The minimum latency possible between app_msi_req and app_msi_ack is one clock cycle. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 190: Msi-X

    Legacy interrupts are signaled on the PCI Express link using message TLPs that are generated internally by the Stratix V Hard IP for PCI Express. The app_int_sts input port controls interrupt generation. When the input port asserts app_int_sts, it causes an Assert_INTA message TLP to be generated and sent upstream.

  • Page 191: Interrupts For Root Ports Using The Avalon-St Interface To The Application Layer

    Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer In Root Port mode, the Stratix V Hard IP for PCI Express receives interrupts through two different mechanisms: ■ MSI—Root Ports receive MSI interrupts through the Avalon-ST RX TLP of type MWr.
  • Page 192 (When signal falls DEASSERT_INTA Message Sent) A2P_MAILBOX_INT6 A2P_MB_IRQ6 A2P_MAILBOX_INT5 A2P_MB_IRQ5 A2P_MAILBOX_INT4 A2P_MB_IRQ4 A2P_MAILBOX_INT3 A2P_MB_IRQ3 A2P_MAILBOX_INT2 A2P_MB_IRQ2 A2P_MAILBOX_INT1 MSI Request A2P_MB_IRQ1 A2P_MAILBOX_INT0 A2P_MB_IRQ0 AV_IRQ_ASSERTED AVL_IRQ MSI Enable (Configuration Space Message Control Register[0]) Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 193: Enabling Msi Or Legacy Interrupts

    CRA slave. After servicing the interrupt, software must clear the appropriate serviced interrupt status bit in the PCI-Express-to-Avalon-MM Interrupt Status register and ensure that no other interrupt is pending. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 194 11–8 Chapter 11: Interrupts Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 195: Chapter 12. Flow Control

    Flow Control: ■ Posted Headers ■ Posted Data Non-Posted Headers ■ ■ Non-Posted Data ■ Completion Headers ■ Completion Data June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 196 There are separate credit allocated registers for the header and data credits. 5. The value in the credit allocated register is used to create an FC Update DLLP. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 197: Throughput Of Non-Posted Reads

    Hard IP for PCI Express and is very difficult to estimate. PCI Express switches can be inserted in this loop, which makes determining a bound on the delay more difficult. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 198 Application Layer and by the maximum read request size that can be issued. The number of header tag values that can be in use is also limited by the Stratix V Hard IP for PCI Express. You can specify 32 or 64 tags though configuration software to restrict the Application Layer to use only 32 tags.

  • Page 199: Chapter 13. Error Handling

    Each PCI Express compliant device must implement a basic level of error management and can optionally implement advanced error management. The Altera Stratix V Hard IP for PCI Express implements both basic and advanced error reporting. Given its position and role within the fabric, error handling for a Root Port is more complex than that of an Endpoint.

  • Page 200: Physical Layer Errors

    Uncorrectable Data Link Layer protocol block in the Data Link Layer (AckNak_Seq_Num) does not correspond to (fatal) an unacknowledged TLP. (Refer to Figure 5–4 on page 5–8.) Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 201: Transaction Layer Errors

    A 64-bit memory transaction which the 32 MSBs of an address are ■ set to 0. A memory transaction that does not match a Windows address ■ June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 202 A TLP in which the type and length fields do not correspond with ■ the total length of the TLP. A TLP in which the combination of format and type is not specified by ■ the PCI Express specification. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 203: Error Reporting And Data Poisoning

    The poisoned bit is set on a received completion TLP. ■ Poisoned packets received by the Hard IP block are passed to the Application Layer. Poisoned transmit TLPs are similarly sent to the link. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 204: Uncorrectable And Correctable Error Status Bits

    Header Log Overflow Status Corrected Internal Error Status Advisory Non-Fatal Error Status Replay Timer Timeout Status REPLAY_NUM Rollover Status Bad DLLP Status Bad TLP Status Receiver Error Status Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 205: Chapter 14. Hard Ip Reconfiguration And Transceiver Reconfiguration

    June 2012 <edit Part Number variable in chapter> This chapter describes features of the Stratix V Hard IP for PCI Express that you can use to reconfigure the core after power-up. It includes the following sections: Hard IP Reconfiguration Interface ■...
  • Page 206 DL_Active state of the Data Link Control and Management state machine. Upstream Port: For upstream ports and components that do not support this optional capability, this bit must be hardwired to 0. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 207 Correctable Error Mask 1.1 compliant cores, this bit should be set to 1. register Table 7–8 on page 7–5, 0x92 Slot Power Limit Scale. b’00 Slot Capability register June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 208 NFTS_SEPCLK. The number of fast training sequences b’10000000 for the separate clock. 0x95 — NFTS_COMCLK. The number of fast training sequences 15:8 b’10000000 for the common clock. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 209 Function supports MSI. b’1 Message Control register for MSI Interrupt pin. b’001 — Reserved. b’00 Table 7–4 on page 7–3, Function supports MSI-X. b’0 Message Control register for MSI June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 210 – 512 ns to less than 1 µs. b’101 – 1 µs to less than 2 µs. b’110 – 2 µs to 4 µs. b’111 – More than 4 µs. 15:3 Reserved. 0x0000 Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 211 BAR4[159:128]. b’0 BAR4[128]: I/O Space. b’0 BAR4[130:129]: Memory Space (see bit settings for b’0 BAR0). 0xA9 BAR4[131]: Prefetchable. b’0 BAR4[159:132]: Bar size mask. b’0 15:4 BAR4[143:132]. b’0 June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 212 Transmit Margin. Directly drives the transceiver tx_pipemargin bits. Refer to the DC and Switching Characteristics for Stratix V Devices to determine what settings are available. 0xB1-FF Reserved. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 213: Transceiver Phy Ip Reconfiguration

    Transceiver Reconfiguration Controller instance and the PHY IP Core for PCI Express instance for a ×4 variant. Figure 14–1. Altera Transceiver Reconfiguration Controller Connectivity Stratix V Hard IP for PCI Express Variant Hard IP for PCI Express Trans-...
  • Page 214 Cores. You must provide a 100–125 MHz free-running clock to the mgmt_clk_clk clock input of the Transceiver Reconfiguration Controller IP Core. Initially, the Stratix V Hard IP for PCI Express requires a separate reconfiguration interface for each lane and each TX PLL. It reports this number in the message pane of its GUI.

  • Page 215: Learning More About Transceiver Phy Reconfiguration

    “Transceiver Reconfiguration Controller” chapter in the Altera Transceiver PHY IP Core User Guide and to Application Note 645: Dynamic Reconfiguration of PMA Controls in Stratix V Devices. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 216 14–12 Chapter 14: Hard IP Reconfiguration and Transceiver Reconfiguration Transceiver PHY IP Reconfiguration Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 217: Chapter 15. Debugging

    Typically, PCI Express hardware bring-up involves the following steps: 1. System reset 2. Linking training 3. BIOS enumeration The following sections, describe how to debug the hardware bring-up flow. Altera recommends a systematic approach to diagnosing bring-up issues as illustrated in Figure 15–1.
  • Page 218 PCIe requires that OCT must be used for proper Receiver Detect with a value of 100 Ohm. You can debug this issue using SignalTap II and oscilloscope. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 219 For example, the Endpoint’s TX signals are connected to the RX pins and the Endpoint’s RX signals are to the TX pins. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 220: Link Hangs In L0 Due To Deassertion Of Tx_St_Ready

    TLP to be less than the InitFC value. analyzer trace to capture PCIe transactions. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...
  • Page 221 RX buffer. For more information about link training, refer to the “Link Training and Status State Machine (LTSSM) Descriptions” section of PCI Express Base Specification 3.0. June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 222 Gen1 and 16000 UI interval for Gen2 3'b111: Absence of Electrical idle exit in 128 us ■ window for Gen1 Transmit de-emphasis selection. The Stratix V Hard IP for txdeemph PCI Express sets the value for this signal based on the [97]...
  • Page 223 2’b01: PHY is in electrical idle. ■ 2’b10: PHY is in loopback mode. ■ 2’b11: Illegal. Not defined. ■ When asserted, the PHY must invert the received data. rxpolarity0 [43] [203] June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...

  • Page 224: Use Third-Party Pcie Analyzer

    Both FPGA programming (configuration) and the initialization of a PCIe link require time. There is some possibility that Altera FPGA including a Hard IP block for PCI Express may not be ready when the OS/BIOS begins enumeration of the device tree.

  • Page 225: Tlp Packet Format Without Data Payload

    (AT) bits in byte 2 of the header and flag the received TLP as malformed if AT is not equal to is 2b’00. The Stratix V Hard IP for PCI Express IP core does not perform this optional check.
  • Page 226 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Stratix V Hard IP for PCI Express June 2012 Altera Corporation...

  • Page 227: Tlp Packet Format With Data Payload

    0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 TD 0 0 0 0 0 0 0 0 0 1 Byte 4 0 0 0 0 First BE Requester ID Byte 8 Address[31:2] Byte 12 Reserved June 2012 Altera Corporation Stratix V Hard IP for PCI Express User Guide...
  • Page 228 Byte 4 Requester ID Message Code Byte 8 Vendor defined or all zeros for Slot Power Limit Byte 12 Vendor defined or all zeros for Slots Power Limit Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

  • Page 229: Additional Information

    Additional Information This chapter provides additional information about the document and Altera. Revision History The table below displays the revision history for the chapters in this User Guide. Date Version Changes Made Added Avalon-MM single dword variant. ■ Added support for Gen3 Programmer Object File (.pof) for Stratix V devices.
  • Page 230 Corrected description of Avalon-MM to PCI Express interrupt registers in Table 7–25 on ■ page 7–13 Table 7–26 on page 7–13. Added ×1, ×4, and ×8 Gen3 support for Stratix V Hard IP for PCI Express with Avalon-ST ■ interface. Added Avalon-MM support in Qsys. ■ November 2011 11.1...
  • Page 231 (software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
  • Page 232 The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. Stratix V Hard IP for PCI Express June 2012 Altera Corporation User Guide...

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