Parallel Decoding - Rigol DS8000-R Series User Manual

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Parallel Decoding

Parallel bus consists of clock line and data line. As shown in the figure below, CLK is
the clock line, whereas Bit0 and Bit1 are the 0 bit and 1st bit on the data line
respectively. The oscilloscope will sample the channel data on the rising edge, falling
edge, or the rising/falling edge of the clock and judge each data point (logic "1" or
logic "0") according to the preset threshold level.
Figure 11-1 Schematic Diagram of Parallel Decoding
In the decode setting menu, click Decode1 → Bus Type to select "Parallel".
1． Enable or disable the bus
Click Bus Status to enable or disable the decoding function.
2． Clock setting (CLK)
Click Clock to enter the clock line setting menu.
Set clock channel
⚫
Click CLK to select any clock channel. The available choices include OFF
and CH1-CH4. The analog channel (CH1-CH4) can be selected as the clock
source. If "OFF" is selected, no clock channel is set, and sampling is
performed when a hop occurs to the data of the data channel during
decoding.
Set the clock edge type
⚫
Click CLK Edge to select the clock edge type. You can select to sample the
channel data on the rising edge (
( ) of the clock signal.
Rising
Falling
Both
falling edge of the clock.
Set the threshold
⚫
11-2
: samples the channel data on the rising edge of the clock.
: samples the channel data on the falling edge of the clock.
: samples the channel data on both the rising edge and the
Chapter 11 Protocol Decoding
), falling edge ( ), or both edges
DS8000-R User Guide