Jtag Chain; Jtag Chain Block Diagram - Xilinx VCK190 Series User Manual

The LED functions can be repurposed with a LEDCR1 register write available via the PHY's
management data interface, MDIO/MDC.
See the TI DP83867 RGMII PHY data sheet at the
details.
The detailed ACAP connections for the feature described in this section are documented in the
VCK190 board XDC file, referenced in

JTAG Chain

[Figure 3, callout 7, 8, and 48]
VCK190 JTAG chain
• J36 2x7 2 mm shrouded, keyed JTAG pod flat cable connector
• J207 USB-C connector connected to U20 FT4232HL USB-JTAG bridge
• U125 XCZU4EG System Controller bank 44
U125
XCZU4EG
BANK 44
TDO
TDI
SYSTEM
CONTROLLER
J53
J36 J51
JTAG
2 mm 2X7
Header
TDO
TDI
U1
U16
ACAP U1
BANK 503
Config
B
JTAG
TDO
U239
IF
TDI
B
See Versal ACAP Configuration
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Appendix B: Xilinx Design
Figure 18: JTAG Chain Block Diagram
TDO
FMC2
N.C.
TDI
TDO
FMC1
N.C.
TDI
U15
B-to-A
S1 S0 OEn
JTAG
A 1A
TDO
L/S
JTAG
MUX
A-to-B
JTAG
A 2A
TDI
L/S
for information on JTAG programming via:
Chapter 3: Board Component Descriptions
Texas Instruments
Constraints.
UTIL_3V3
R88 R87
4.70K 4.70K
SW3
SW3 SS
1 2 01
ON ON 00
CH1 SYSCTLR JTAG
ON OFF 01
CH2 FT4232 JTAG
UTIL 3v3
1
2
R97
3 499
1B1
SYSCTLR_VERSAL_TDO
1B2 FT4232_TDO
1B1
SYSCTLR_VERSAL_TDI
2B2
FT4232_TDI
Send Feedback
website for component
Set SW3
to
"ON OFF"
R98
499
U20
TDO
FT4232HL
UART
BRIDGE
TDI
www.xilinx.com
J207
U
S
B
X23204-100719
44