Xilinx VCK190 Series User Manual page 10

• PL FMCP HSCP (FMC+) connectivity
XPIO triplet 3 (banks 706, 707, 708)
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FMCP1 HSCP full LA[00:33] bus
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FMCP2 HSCP full LA[00:33] bus
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• PL GPIO connections
PL UART1 to FTDI
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PL GPIO DIP switch (4-position)
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PL GPIO pushbuttons (two)
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PL GPIO LEDs (four)
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PL GPIO DC configuration header
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PL SYSCTLR_GPIO[0:5]
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• 44 PL GTY transceivers (11 quads)
PCIe 8-lane edge connector (8, banks GTY103, GTY104)
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HSDP USB3.1 TYPE C (1, bank GTY105)
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zSFP28 (2, bank GTY105)
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HDMI (3, bank GTY106)
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HDMI TX only, RX not used (1, bank GTY106)
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zQSFP28 (4, bank GTY200)
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FMCP1 HSCP DP (12, banks GTY201-GTY203)
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FMCP2 HSCP DP (12, banks GTY204-GTY206)
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Not used (1, bank GTY105)
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• PCI Express endpoint connectivity
Gen1 8-lane (x8)
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Gen2 8-lane (x8)
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Gen3 8-lane (x8)
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Gen4 8-lane (x8)
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• PS PMC MIO connectivity
PS MIO[0:12]: boot configuration header
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- DC QSPI support
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Chapter 1: Introduction
www.xilinx.com
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