Clock Generation; Clock Sources; Programmable Ddr4 Dimm Si570 Clock - Xilinx VCK190 Series User Manual

• FTDI FT4232 USB-to-JTAG/USB-UART device (U20) connected to USB 3.1 type-C connector
(J207)
• JTAG pod flat cable connector J36 (2 mm 2x7 shrouded/keyed)
See the "FT4232HL UART Interface Connections" figure in
overview of FT4232 U20 JTAG and USB-UART connectivity.

Clock Generation

The VCK190 board provides fixed and variable clock sources for the XCVC1902 U1 ACAP and
other function blocks. The following table lists the source devices for each clock.
Table 17: Clock Sources
Callout
36
37
38
39
40
41
42
43
44
45
46
47
The connection details for ACAP U1 connected clocks described in this section are documented
in the VCK190 board XDC file, referenced in

Programmable DDR4 DIMM SI570 Clock

[Figure 3, callout 36]
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Ref. Des.
U2 DDR4 DIMM CLK, 200 MHz, 3.3V
LVDS, 0x60
U3 LPDDR4 CLK2, 200 MHz, 3.3V
LVDS, 0x60
U4 LPDDR4 CLK1, 200 MHz, 3.3V
LVDS, 0x60
U5 HSDP CLK, 156.25 MHz, 3.3V
LVDS, 0x5D
U32 ACAP U1 REF CLK, 33.33 MHz,
1.8V CMOS, 0x5D
U39 PCIe jitter atten., 100 MHz, 3.3V
LVDS
U62 HDMI jitter atten., 148.50 MHz,
3.3V LVDS, 0x6C
U142 SYSCTLR clocks 33.33 MHz & 125
MHz I2C 0x6A
U192 zSFP CLK, 156.25 MHz, 3.3V
LVDS, 0x5D
U205 FMCP MGT CLK, 100 MHz, 3.3V
LVDS, 0x5F
U219 IEEE-1588 eCPRI CLK, various,
3.3V, 0x58
J328-J331 IEEE-1588 eCPRI 8A34001 CLK in
and out SMA pairs
Chapter 3: Board Component Descriptions
PMC MIO[42:43] UART0
Feature
Silicon Labs SI570BAB000299DG
Silicon Labs SI570BAB000299DG
Silicon Labs SI570BAB000299DG
Silicon Labs SI570BAB000544DG
Silicon Labs SI570JAC000900DG
IDT 85411AMLF
IDT 8T49N241-994NLGI
Silicon Labs Si5332FD10259-
GM1
Silicon Labs SI570BAB000544DG
Silicon Labs SI570BAC002038DG
IDT 8A34001E-000AJG8
Rosenberger 32K10K-400L5
Appendix B: Xilinx Design
Send Feedback
for an
Schematic
Notes
Page
4
5
7
8
43
49
52
101
8
48
104
104
Constraints.
www.xilinx.com
45