Programmable Lpddr4 Si570 Clock2; Programmable Lpddr4 Si570 Clock1 - Xilinx VCK190 Series User Manual

The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator
(U2) connected to the GC inputs of U1 DDR4 DIMM interface bank 700. The
DDR4_DIMM1_CLK_P and DDR4_DIMM1_CLK _N series capacitor coupled clock signals are
connected to XCVC1902 ACAP U1 pins AE42 and AF43, respectively. At power-up, this clock
defaults to an output frequency of 200.000 MHz. User applications or the System Controller can
change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus
interface. Power cycling the VCK190 board reverts this user clock to the default frequency of
200.000 MHz.
• Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range,
200.000 MHz default)
• I2C address 0x60
• LVDS differential output, total stability: 61.5 ppm

Programmable LPDDR4 SI570 Clock2

[Figure 3, callout 37]
The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator
(U3) connected to the GC inputs of U1 LPDDR4_2 interface bank 705. The LPDDR4_CLK2_P
and LPDDR4_CLK2_N series capacitor coupled clock signals are connected to XCVC1902 ACAP
U1 pins AW27 and AY27, respectively. At power-up, this clock defaults to an output frequency
of 200.000 MHz. User applications or the System Controller can change the output frequency
within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the
VCK190 board reverts this user clock to the default frequency of 200.000 MHz.
• Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range,
200.000 MHz default)
• I2C address 0x60
• LVDS differential output, total stability: 61.5 ppm

Programmable LPDDR4 SI570 Clock1

[Figure 3, callout 38]
The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator
(U4) connected to the GC inputs of U1 LPDDR4_1 interface bank 705. The LPDDR4_CLK1_P
and LPDDR4_CLK1_N series capacitor coupled clock signals are connected to XCVC1902 ACAP
U1 pins AK8 and AK7, respectively. At power-up, this clock defaults to an output frequency of
200.000 MHz. User applications or the System Controller can change the output frequency
within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the
VCK190 board reverts this user clock to the default frequency of 200.000 MHz.
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Chapter 3: Board Component Descriptions
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