System Reset Por_B - Xilinx VCK190 Series User Manual

• Part number: MT53D512M32D2DS-046 WT:D (dual die LPDDR4 SRAM)
• Component description
16 Gb (512 Mb x 32)
○
1.1V 200-ball WFBGA
○
DDR4-2133
○
The VCK190 XCVC1902 ACAP PL DDR interface performance is documented in the Versal Prime
Series Data Sheet: DC and AC Switching Characteristics (DS956). The VCK190 board LPDDR4
component memory interfaces adhere to the constraints guidelines documented in the PCB
guidelines for DDR4 section of Versal ACAP PCB Design User Guide (UG863). The VCK190 DDR4
component interface is a 40Ω impedance implementation. Other memory interface details are
also available in the Versal ACAP Memory Resources Architecture Manual (AM007). For more
memory component details, see the Micron MT53D512M32D2DS data sheet at the
website. The detailed ACAP connections for the feature described in this section are
documented in the VCK190 board XDC file, referenced in

System Reset POR_B

[Figure 3, callout 35]
POR_B is the Versal ACAP processor reset, which can be controlled by:
• SYSCTLR (U125)
• PC4 header (J36)
• MIO EBM (external boot module on J212)
• FTDI USB JTAG chip (U20)
In the following figure, U235 allows directional open drain level shifting for all of these masters,
and J326 allows them to be bused together if desired. The fifth channel buffers POR_B out to
the EBM (external boot module) as DC_PS_POR_B. The TPS389001 U10 supervisor chip holds
POR_B off until power is valid. The VCK190 board POR circuit is shown in the figure.
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Chapter 3: Board Component Descriptions
Appendix B: Xilinx Design
Send Feedback
Micron
Constraints.
www.xilinx.com
27