Xilinx VCK190 Series User Manual page 51

Table 18: GTY Mapping (cont'd)
SFP1
SFP0
None
HSDP (USB-C)
HSDP SI570 CLK
zSFP SI570 CLK
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
None
PCIe Slot Clock 0
(buffered)
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
NONE
PCIe Slot Clock 0
(buffered)
The GTY connections are shown in the following figure.
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
VCK190 XC10S80 VSVA2197 GTY Mapping
ch3 PCIe
ch2
ch1
GTYT_M
ch0
Quad 105
refclk1
refclk0
ch3
ch2
ch1
GTYB_M
PCIe
ch0 Quad 104
refclk1
refclk0
ch3
ch2
ch1
GTYT_S
CPMG4
ch0
Quad 103
refclk1
refclk0
CPMG4
Chapter 3: Board Component Descriptions
PCIe ch3
ch2
ch1
GTYT_S
ch0
Quad 205
refclk1
refclk0
ch3
ch2
ch1
GTYB_S
MRMAC
Quad 204 ch0
refclk1
refclk0
ch3
ch2
ch1
GTYT_M
MRMAC
ch0
Quad 203
refclk1
refclk0
ch3
ch2
ch1
GTYB_M
PCIe
Quad 202
ch0
refclk1
refclk0
ch3
ch2
ch1
GTYT_S
MRMAC
ch0
Quad 201
refclk1
refclk0
ch3
ch2
ch1
GTYB_S
MRMAC
Quad 200
ch0
refclk1
refclk0
Send Feedback
FMC2 DP7
FMC2 DP6
FMC2 DP5
FMC2 DP4
FMC2_GBTCLK1
SI570_8A34001_MUX_BU
F2
FMC2 DP3
FMC2 DP2
FMC2 DP1
FMC2 DP0
FMC2_GBTCLK0
SI570_8A34001_MUX_BU
F1
FMC1 DP11
FMC1 DP10
FMC1 DP9
FMC1 DP8
FMC1_GBTCLK2
None
FMC1 DP7
FMC1 DP6
FMC1 DP5
FMC1 DP4
FMC1_GBTCLK1
None
FMC1 DP3
FMC1 DP2
FMC1 DP1
FMC1 DP0
FMC1_GBTCLK0
SI570_8A34001_MUX_BU
F0
QSFP4
QSFP3
QSFP2
QSFP1
IEEE-1588 Clock
IEEE-1588 Clock
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