Si5341B 10 Independent Output Any-Frequency Clock Generator U43; Inputs - Xilinx Zynq UltraScale+ ZCU216 User Manual

Table 18: Clock Connections to ZU49DR U1 (cont'd)
Clock Source Ref. Des. and Pin
J7
U409 8A34001 eCPRI Clock
U409.A9 (Q1)
U409.B9 (Q1)
U409.A11 (Q2)
U409.B11 (Q2)
U409.A12 (Q3)
U409.B12 (Q3)
U409.M8 (Q7)
U409.L8 (Q7)
U409.A6 (Q8)
U409.B6 (Q8)
U409.M6 (Q11)
U409.L6 (Q11)
Notes:
1. U1 ZU49DR Bank 503 supports LVCMOS18 level inputs.
2. Series capacitor coupled, U1 MGT (I/O standards do not apply).
3. Series capacitor coupled.

SI5341B 10 Independent Output Any-Frequency Clock Generator U43

[Figure 2, callout 10]
• Clock generator: Silicon Labs SI5341B-D07833-GM
• Jitter: <100 fs RMS typical
• Differential and single-ended outputs
The SI5341B data sheet addendum for the Silicon Labs SI5341B-D07833-GM documents the
pre-programmed output frequencies:

• Inputs:

XAXB: 48 MHz
○
Crystal Mode
○
IN0: Unused
○
IN1: Unused
○
IN2: Unused
○
FB_IN: Unused
○
UG1390 (v1.1) July 10, 2020
ZCU216 Board User Guide
Chapter 3: Board Component Descriptions
Net Name
USER_SMA_MGT_CLOCK_N
8A34001_Q1_OUT_P
8A34001_Q1_OUT_N
8A34001_Q2_OUT_P
8A34001_Q2_OUT_N
8A34001_Q3_OUT_P
8A34001_Q3_OUT_N
8A34001_Q7_OUT_P
8A34001_Q7_OUT_N
8A34001_Q8_OUT_P
8A34001_Q8_OUT_N
8A34001_Q11_OUT_P
8A34001_Q11_OUT_N
I/O Standard ZU49DR (U1) Pin
2 M35
2
2
LVDS AT23
LVDS AT24
LVDS H30
LVDS G30
2
2
LVDS
LVDS H21
2
2
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Y39
Y40
T34
T35
J21
Y34
Y35
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