Xilinx Zynq UltraScale+ ZCU216 User Manual page 7

USB-to-JTAG Bridge
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PC4 2x7 2 mm JTAG pod flat cable header
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• Clocks
GTR_REF_CLK_USB3 26 MHz
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GTR_REF_CLK_SATA 125 MHz
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CLK104 (various frequencies):
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- CLK104_PL_CLK
- CLK104_PL_SYSREF
- CLK104_AMS_SYSREF
- CLK104_DDR_PLY_CAP_SYNC
- CLK104_ADC_REFCLK
- CLK104_DAC_REFCLK
8A34001 1588 eCPRI (various frequencies):
○
- 8A34001_Q1_OUT
- 8A34001_Q2_OUT
- 8A34001_Q3_OUT
- 8A34001_Q7_OUT
- 8A34001_Q8_OUT
- 8A34001_Q11_OUT
CLK_100 100 MHz
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CLK_125 125 MHz
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PS_REF_CLK 33.33 MHz
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USER_MGT_SI570 (default 156.25 MHz)
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USER_SI570_C0 (default 300 MHz)
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USER_SI570_C1 (default 300 MHz)
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ADC_CLK_225 (direct connect SMAs)
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DAC_CLK_229 (direct connect SMAs)
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USER_MGT_SMA_CLK (series capacitor connected SMAs)
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• PS DDR4 4 GB 64-bit SODIMM
• PL DDR4 C0 I/F 2 GB 32-bit Component (4x8-bit)
UG1390 (v1.1) July 10, 2020
ZCU216 Board User Guide
Chapter 1: Introduction
www.xilinx.com
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